Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-11-17
2002-02-26
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S163000, C370S516000
Reexamination Certificate
active
06351508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to telecommunications. More particularly, the invention relates to a circuit for removing “jitter” from a recovered clock signal in a telecommunications network.
2. State of the Art
The first commercial digital voice communications system was installed in 1962 in Chicago, Ill. The system was called “T1” and was based on the time division multiplexing (TDM) of twenty-four telephone calls on two twisted wire pairs. The digital bit rate of the T1 system was 1.544 Mbit/sec (±200 bps), which was, in the nineteen sixties, about the highest data rate that could be supported by a twisted wire pair for a distance of approximately one mile. The cables carrying the T1 signals were buried underground and were accessible via manholes, which were, at that time in Chicago, spaced approximately one mile (actually, 6,000 ft.) apart. Thus, analog amplifiers with digital repeaters were conveniently located at intervals of approximately one mile.
Thy T1 system is still widely used today and forms a basic building block for higher capacity communication systems such as T3 which transports twenty-eight T1 signals. The designation T1 was originally coined to describe a particular type of carrier equipment. Today T1 is often used to refer to a carrier system, a data rate, and various multiplexing and framing conventions. While it is more accurate to use the designation “DS1” when referring to the multiplexed digital signal formed at an 8 KHz rate and used to carry twenty-four voice channels by the T1 carrier, the designations DS1 and T1 are often used interchangeably. Today, T1 /DS1 systems still have a data rate of 1.544 Mbit/sec and support up to twenty-four voice and/or data DS0 channels. Similarly, the designations DS2 and T2 both refer to a system transporting up to four DS1 signals (96 DS0 channels) and the designations DS3 and T3 both refer to a system transporting up to seven DS2 signals (672 DS0 channels). The timing tolerance for modern T1 equipment has been narrowed to ±50 bps. The T1 and T2 standards are utilized in North America and Japan. Similar, but incompatible, standards called E1 and E2 are utilized in Europe. The T3 standard is utilized in North America and a similar, but incompatible, standard called E3 is utilized in Europe. In the 1980s, fiber optic technology called SONET (synchronous optical network) provided a measure of compatibility between T3 and E3 by allowing both to be mapped into an STS-1 signal.
The current standard for T1/DS1 systems incorporates many improvements and enhancements over the original T1 system. The basic T1 system is based on a frame of 193 bits, i.e. twenty-four 8-bit channels (the payload) and one framing bit (F). According to today's standards, the 192 bit payload need not be “channelized” into 24 DS0 channels. In addition, superframe and extended superframe formats have been defined (as is known in the art).
In addition to modern framing conventions, the present T1 specification also includes provisions for different “line codes”, sometimes referred to as “transmission codes”. It will be appreciated that the T1 signal is a plesiochronous (tightly controlled asynchronous) signal and, unlike a synchronous (SONET) signal, is still subject to wander, jitter, and slips. Line codes are signalling conventions which are designed to facilitate frame synchronization and error detection.
Asynchronous Transfer Mode (ATM) is a packet oriented technology which permits continuous bit rate signals carrying one or more of voice, video, and data, to be conveyed across a network within packets. ATM is suitable for the transport of bursty traffic such as data, as well as accommodating constant or continuous bit rate signals. In delivering continuous bit rate traffic (e.g., T1, DS3 signals) in a broadband network, the clock controlling the destination node buffer must operate at a frequency precisely matched to that of the service signal input at the source node in order to avoid buffer overflow or underflow and resulting loss of data. However, the clock frequency at the destination node cannot easily be traced directly back to that of the source, because the ATM network inherently introduces cell jitter; i.e., random delay and aperiodic arrival of cells at a destination node, which corrupts the value of the cell arrival times and makes their use more difficult as a means for directly recovering the original service signal input frequency.
Clock recovery can be provided by a timestamp or an adaptive clock. The first method is called the synchronous residual timestamp (SRTS). The SRTS method assumes the presence of a common synchronous network clock from which both the sender and the receiver can reference. In the adaptive clock method, the receiver buffers incoming traffic and compares the level of the buffer with a local clock. The level of the buffer is used to control the frequency of the clock.
Prior Art
FIG. 1
illustrates a typical arrangement of a Phase Lock Loop (PLL) circuit for clock dejitter. The circuit
10
includes a FIFO buffer
12
, a voltage controlled oscillator (VCXO)
14
, a filter
16
, and a circuit
18
which is used to control the VCXO
14
via a signal applied to the filter
16
. Received data is written into the FIFO using the (recovered clock) RCLK signal and reads data out using the dejittered clock signal produced by the VCXO. If the VCXO and the RCLK are not the same speed, the FIFO will either underflow or overflow. The circuit
18
attempts to adjust the VCXO in response to FIFO underflow/overflow. Exemplary circuits for controlling a VCXO via a filter in response to overflow and underflow flags are disclosed in U.S. Pat. Nos. 4,961,188, 5,007,070, and 5,471,511. In general, the circuits used to control the VCXO include numerous counters and multiplexers which compare overflow and underflow to thresholds and set the VCXO to various thresholds accordingly. The circuits are cumbersome, complex, and expensive.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a circuit for removing “jitter” from a recovered clock signal in a telecommunications network.
It is also an object of the invention to provide a circuit for controlling a VCXO so that it closely matches the recovered clock in a telecommunications network.
It is another object of the invention to provide a compact and simple circuit for controlling a VCXO.
In accord with these objects which will be discussed in detail below, the circuit of the present invention is intended to be used with a FIFO buffer having overflow and underflow flags, a filter, and a voltage controlled oscillator (VCXO). The circuit of the invention includes two D-Q flip-flops, an OR gate, and an XNOR (exclusive NOR) gate. The underflow and overflow flags from the FIFO are coupled to the inputs of the OR gate and the Q outputs of the flip-flops are coupled to the inputs of the XNOR gate. The Qb output of each flip-flop is coupled to the D input of the respective flip-flop. The recovered clock signal is coupled to the clock input of the first flip-flop and the output of the VCXO is coupled to the clock input of the second flip-flop. The SET input of the first flip-flop is coupled to the overflow flag and the RESET input of the first flip-flop is coupled to the underflow flag . The SET input of the second flip-flop is coupled to the output of the OR gate and the output of the XNOR gate is passed through the filter to the input of the VCXO.
The circuit operates both as a phase detector and a frequency detector. If the average frequency of the recovered clock is equal to the dejittered clock frequency (the output of the VCXO), then the circuit acts as a phase detector with the two flip-flops acting as divide-by-two circuits. When phase-locked (90° shifted), the output of the XNOR will have a 50% duty cycle. If the recovered clock is more than 90° ahead of the dejittered clock, then the XNOR output will be high more than 50% of the time which will cause the VCXO to run faster due to the increasi
Shishkoff Alexis
Stakely Barry L.
Chin Stephen
Fan Chieh M.
Gallagher Thomas A
Gordon David P
Jacobson David S
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