Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2001-04-19
2002-06-18
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S314000, C438S319000
Reexamination Certificate
active
06406965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating integrated circuits, and more particularly, to a method of fabricating heterojunction bipolar transistors (HBTs) having extremely high speed at very low currents.
2. Description of the Prior Art
U.S. Pat. 5,486,483 and 5,804,487, issued to the inventor, teach methods for forming semiconductor devices such as HBTs permitting achievement of highly controllable spacing between an emitter mesa and base ohmic contact metal of the HBT. This spacing is an important factor in providing good performance of the device. It is now desirable to further develop such HBTs to operate at the highest possible speed while achieving a small individual device current. This will permit a large number of high-speed devices to be formed on a single chip while still maintaining a reasonable chip power level.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating an HBT having extremely high speed at the lowest possible current.
Briefly, the present invention provides a method for forming very high speed HBTs with low power consumption by providing an arrangement for achieving extremely small emitter area and extremely small base area, with a large portion of both the emitter area and the base area being contacted with metal. In conjunction with this, the collector metal contact can be closely spaced to the emitter to achieve a low parasitic collector resistance. To achieve this in accordance with one embodiment of the invention, a collector layer, a base layer and an emitter layer are formed in a stacked arrangement on a substrate. A layer of material is then deposited on the emitter layer, a first photoresist is formed over a portion of the material, and the layer of material and the emitter layer are etched using the first photoresist as a mask to form an emitter mesa on the base layer. At this point, the material remains on top of the emitter mesa and the first photoresist remains on top of the material. Next, a second photoresist is deposited on the base layer. The second photoresist is patterned and developed on the base layer to expose a portion of the base layer surrounding the emitter mesa. A base ohmic metal is then formed on the first and second photoresists and the exposed portion of the base layer. The first and second photoresists, with the base ohmic material thereon, are lifted off, leaving the base ohmic material on the base layer. By virtue of the preceding steps, the base ohmic material is uniformly spaced relative to the emitter mesa. Next, the emitter mesa and a portion of the base ohmic metal is covered with a third photoresist. The base layer is then etched to undercut the base ohmic metal, thereby reducing the size of the base layer and, correspondingly, significantly reducing the base-collector parasitic capacitance.
REFERENCES:
patent: 5024958 (1991-06-01), Awano
patent: 5268315 (1993-12-01), Prasad et al.
patent: 5296389 (1994-03-01), Shimawaki
patent: 5486483 (1996-01-01), Lammert
patent: 5804487 (1998-09-01), Lammert
Antonelli Terry Stout & Kraus LLP
Nguyen Tuan H.
TRW Inc.
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