Compact trench capacitor memory cell with body contact

Details Compact trench capacitor memory cell with body contact Compact trench capacitor memory cell with body contact

2001-05-25

2002-08-20

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

06437388

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to semiconductor devices, and more particularly, to a semiconductor device having memory array active areas formed using annular shapes and including body contacts formed between transistor devices and connecting to dopant wells formed in a substrate.
2. Description of the Related Art
Semiconductor memory devices, which include vertical transistors often rely on outdiffusion from buried straps to form a connection between a deep trench storage node and a pass transistor. As shown in
FIG. 1
, a top view of a partially fabricated dynamic random access memory chip
110
is shown. Four memory cells are depicted; each memory cell includes a deep trench
114
. Active areas
116
include diffusion regions. Adjacent to active areas
116
are formed isolation trenches
118
filled with a dielectric material. A buried strap
120
is shown for one of the memory cells
112
. A collar
122
of an adjacent cell and two adjacent isolation trenches
118
form a three-sided isolation region encapsulating buried strap
120
.
Referring to
FIG. 2
, a cross-sectional view, taken at section line
2
—
2
of
FIG. 1
, is shown. Memory cell
112
includes a vertical transistor
126
employed for accessing a storage node
128
in deep trench
114
. When scaling down sizes of memory cells, buried strap
120
outdiffusion regions begin to extend as far as a neighboring memory cell's collar regions
123
. Buried strap
120
may form an extended outdiffusion region
130
, which may extend to the collar
123
of a neighboring memory cell
121
. If contact is made with the neighboring cell's collar
122
by region
130
, pinch-off of the access transistor
126
begins to occur. For memory cells which feature vertical access transistors surrounded by a 3-sided isolation, as shown in
FIG. 1
, floating body effects may arise, similar to those encountered in silicon on insulator structures, if the buried strap's outdiffusion
130
reaches the opposite isolating collar
122
and pinches off the contact to the transistor body.
Floating body effects are caused when the body of a transistor gets electrically isolated from a conductive medium by either an insulator or an area with opposite doping or a depletion region associated with the outdiffusion junction. In silicon on insulator (SOI) transistor structures, an insulator separates two silicon structures, one of which includes a channel region of the transistor device (e.g., transistor body). The potential at the transistor channel cannot be set to a specific value, but changes according to the voltage conditions applied to the adjacent source/drain junctions (i.e., the transistor channel voltage is floating and adjusts thermodynamically to its surroundings). Hence, the transistor threshold voltage changes with varying body bias, leading to parasitic leakage from the transistor. This is undesirable since gate control of the transistor devices is reduced.
Similar effects, as described above with reference to
FIGS. 1 and 2
, are encountered in vertical transistor structures if the transistor body is disconnected from the silicon substrate by a lower source/drain junction. In other structures, outdiffusion from buried straps on adjacent memory cells may face each other and share a common active area. In these designs, outdiffusion may short storage nodes of adjacent structures. In these designs, isolation regions may be desirable to prevent shorting out these storage nodes; however, this would divide the active area into two portions, cause floating body problems and require additionally processing steps.
Therefore, a need exists for a structure and method for forming a structure, which reduces or eliminates floating body potentials in memory devices with vertical transistors, improves gate control of the vertical transistors, provides compact memory cells and prevents storage node shorts due to outdiffusions of buried straps.
SUMMARY OF THE INVENTION
A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.
In other embodiments, the body contact preferably includes doped polysilicon, which outdiffuses into the diffusion well to form a connection to the diffusion well. The semiconductor device may include a dielectric spacer formed along vertical sidewalls of the body contact to prevent electrical connection between the at least two active areas. The body contact may include a doped polysilicon divot spacer formed adjacent to the at least two active areas through the dielectric spacer, and the doped polysilicon divot spacer outdiffuses into the at least two active areas to form a connection to the at least two active areas. Each of the at least two active areas preferably forms an annular ring around the trench. The semiconductor device may include a dielectric layer formed on top of the body contact. A bitline contact may be formed between the gates on the dielectric layer. The bitline contact may connect to at least one of the at least two active areas.
A method for fabricating a semiconductor device includes forming a trench capacitor in a substrate and forming a gate conductor in the trench, which is electrically isolated from the trench capacitor. A first dielectric layer is formed over the gate conductor and portions of the substrate are exposed surrounding the first dielectric layer over the gate conductor. Dopants are implanted in a region surrounding the trench to form an active region around the trench. The active region of the substrate is etched to form a vertical portion. surrounding the trench. A body contact is formed adjacent to the vertical portion which electrically connects the vertical portion to a well formed below the vertical portion in the substrate to prevent floating body effects in a transistor formed by the vertical portion.
In other methods, the step of forming the first dielectric layer may include forming sidewall spacers around sidewalls of the gate conductor after the step of implanting dopants. The step of forming a trench capacitor may include the step of forming trenches in the substrate using a first lithographic mask pattern. The step of implanting dopants may include the step of forming active areas in the substrate using the first lithographic mask pattern to form annular active areas about the trenches. The step forming the body contact may also include forming a dielectric spacer along vertical sidewalls of the body contact. The body contact preferably includes a doped polysilicon divot spacer formed adjacent to the active area through the dielectric spacer.
In still other methods, the step of outdiffusing dopants of the doped polysilicon divot spacer into the active area is preferably performed to form a connection to the active area. The body contact may include doped polysilicon and dopants of the doped polysilicon may be outdiffused into the well to form a connection to the well. A dielectric layer may be formed on top of the body contact and a bitline contact is formed self-aligned between adjacent gates conductor to connect to the active area to a bitline.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5252845 (1993-10-01), Kim et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 6172390 (2001-01-01), Rupp et al.
patent: 6355529 (2002-03-01), Heo et al.
patent: 6365452 (20

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