Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-24
2002-11-26
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C430S005000, C378S035000, C700S103000, C700S105000, C700S120000, C700S121000
Reexamination Certificate
active
06487712
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims the priority of Korean patent application Serial No. 99-46436 filed on Oct. 25, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a mask for conductive wirings in a semiconductor device, and more particularly, a method of manufacturing a mask for conductive wirings in a semiconductor device which is adapted to more easily perform a planarization process for an interlayer insulating film formed on the upper portion of conductive wirings for interconnecting respective elements disposed on a semiconductor substrate.
2. Description of the Related Art
Currently, as the development of semiconductor devices follows a trend toward an increased capacity and a highly integrated degree, an area of the semiconductor devices becomes reduced increasingly, and consequently, a metal wiring within the semiconductor devices and the width thereof are reduced. There is therefore a need for a conductive wiring structured of several layers together with this structure.
In order to construct such a conductive wiring into several layers, and, at the same time, to minimize the size of the conductive wirings, it is necessary that an interlayer insulating film formed on the upper portion of a lower conductive wiring should be planarized. The aim of this planarization for the interlayer insulating film is to improve the depth of a focus in the process of development of a light sensitive film for patterning an upper conductive wiring. Also, such a planarization process is a requisite for depositing a film made of tungsten and performing successively a CMP (Chemical-Mechanical Polishing) process when forming a tungsten plug to bury a contact.
In the meantime, a process of manufacturing a mask for a conventional semiconductor device will be described hereinafter with respect to the present invention.
First, a layout for a circuit to be formed is designed, and the layout for the circuit is to calculate the size of a physical device generating an electrical parameter according to the formation of the circuit. In the process of this layout, the size in length of a designed drawing for a circuit determines the thickness of a layer to be deposited by CVD or to be doped, and the vertical size thereof determines the size of a wafer pattern, which become a basis for a reduced drawing of a resultant circuit called a composite drawing.
After the completion of the layout, a digitizing process is performed for determining a coordinate of a drawing in which a semiconductor circuit is designed to fabricate a mask. That is, the drawing is positioned on an X-Y board in which a cursor is connected to a computer, and the cursor reads the size, shape and position of each pattern in the drawing to store them in a memory of the computer. This information on the pattern is used for fabrication of a reticle or in an Ebeam driving system.
When such a digitizing process is completed, the pattern is copied to form a mask, which is called the reticle. This reticle is an emulsion plate or a chrome thin film selectively exposed to a light from a pattern generator (PG). The pattern generator (PG) consists of a light source and a high-speed shutter which is controlled by a computer, and the pattern is developed to form opaque and transparent areas on a surface of the reticle like a photo film development. The pattern of the reticle is transferred to a mask on which a photoresist having a uniform thin film is coated by the light source.
By using the mask fabricated through the above-mentioned processes, conductive wirings of a semiconductor device are formed. If another upper conductive wiring is formed to form a multi-layered conductive wiring, an interlayer insulating film is formed on a conductive wiring formed previously, followed by a planarization process being performed on the interlayer insulating film.
Meanwhile, in performing such a planarization process, an interval between respective conductive wirings formed in the same layer determines whether or not the planarization process will be performed successively, which will be described hereinafter with reference to FIG.
1
.
FIG. 1
is a top view illustrating a mask
40
used for forming conductive wirings in a typical semiconductor device according to the prior art.
In
FIG. 1
, each conductive wiring pattern (chrome pattern) is formed on a conventional typical a mask
40
for conductive wirings according to the type of a conductive wiring to be formed on a glass substrate
40
. Conductive wirings are formed on a semiconductor substrate through a patterning process using this mask
40
.
FIG. 2A
is a cross-sectional views illustrating a semiconductor device in which conductive wirings are formed using the mask
40
shown in
FIG. 1
, followed by forming an another interlayer insulating layer to form upper conductive wirings according to the prior art.
Referring to
FIG. 2A
, after a first interlayer insulating layer
52
has been formed on a top surface of the a semiconductor substrate
51
, respective conductive wirings
53
-
1
,
53
-
2
, and
53
-
3
are formed on the first interlayer insulating layer
52
by using the mask
40
shown in FIG.
1
. Then, a second interlayer insulating layer
54
is formed on the first interlayer insulating layer
52
and the respective conductive wirings
53
-
1
,
53
-
2
, and
53
-
3
to build a structure having the shape as shown in FIG.
2
A.
In the state in which this process is completed, in order to form another upper conductive wiring on the second interlayer insulating layer
54
, it is necessary that the planarization process should be performed on the second interlayer insulating layer
54
.
FIG. 2B
is a cross-sectional view illustrating a semiconductor device in the state in which a CMP process for the planarization is performed on the structure as shown in
FIG. 2A
, and the top surface of the second interlayer insulating film
54
is washed.
As shown in
FIG. 2A
, dishings occur on the top surfaces of the second interlayer insulating film
54
corresponding to the region between the conductive wirings
53
-
1
and
53
-
2
spaced apart at a minimum interval and the region between the conductive wirings
53
-
2
and
53
-
3
among the conductive wirings
53
-
1
,
53
-
2
and
53
-
3
, so that the planarization for the second interlayer insulating film
54
is not accomplished normally.
Furthermore, though the dishing formed corresponding to the region between the conductive wirings
53
-
1
and
53
-
2
is eliminated by the planarization process, in the case of the dishing formed corresponding to the region between the conductive wirings
53
-
2
and
53
-
3
shown in
FIG. 2B
, the top surface of a region of the interlayer insulating film
54
where a difference in a space between the conductive wirings is greater has a deeper step portion when compared with the top planar surface of the remaining regions of the interlayer insulating film
54
. As a result, there has been a problem in that since a pad of CMP equipment is out of contact with the top surface of the region of the interlayer insulating film
54
having the deeper step formed therein, it is very difficult to achieve a complete planarization for the interlayer insulating film
54
according to the density of the conductive wirings and shape of arranged conductive wirings in a semiconductor chip (semiconductor device).
In the meantime,
FIGS. 3A and 3B
are cross-sectional views illustrating a semiconductor device for which another planaraization process has been performed using a separate step compensating layer in order to resolve the above conventional problem.
First, in
FIG. 3A
, after a first interlayer insulating film
62
has been formed on a semiconductor substrate
61
, respective conductive wirings
63
-
1
,
63
-
2
, and
63
-
3
are formed thereon by using the mask
40
as shown in
FIG. 1. A
second interlayer insulating film
64
is then formed on the conductive wirings
63
-
1
,
63
-
2
, and
63
-
3
and the first interl
Dongbu Electronics Co. Ltd.
Keefer Timothy J.
Kik Phallaka
Wildman Harrold Allen & Dixon
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