Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-03
2002-12-31
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S306000
Reexamination Certificate
active
06501113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device suitable for a DRAM (dynamic random access memory) having a capacitor (capacitive element): employing a high dielectric film or an SRAM (static random access memory) having a capacitor employing a ferroelectric film and a method of manufacturing the same.
2. Description of the Background Art
First, a term employed in this specification is described. Throughout the specification, the term “noble metal” stands for a metal belonging to a group consisting of gold, silver and the platinum metals (Ru, Rh, Pd, Os, Ir and Pt).
A DRAM is generally known as a semiconductor memory device capable of inputting/outputting stored information at random. In general, such a DRAM has a memory cell array serving as a storage area storing numerous information and a peripheral circuit necessary for inputting/outputting the information from/to an external device. A group of memory cells is arranged on the memory cell array, occupying a large area in a semiconductor chip, in the form of a matrix.
A known memory cell for storing unitary memory information has a single MOS (metal oxide semiconductor) transistor and a single capacitor connected thereto. Such a memory cell is referred to as a one-transistor one-capacitor memory cell. This type of memory cell having a simple structure can readily improve the degree of integration of the memory cell array, and is hence widely employed in a DRAM having a large capacity.
Memory cells of the DRAM are classified into some types depending on capacitor structures. A known capacitor is referred to as a stacked capacitor. A principal part of the stacked capacitor is extended onto a gate electrode or a field oxide film, thereby ensuring a large facing area between electrodes.
Due to the aforementioned characteristic, the stacked capacitor can ensure a high capacitance also when elements are refined following integration of the semiconductor memory device. Therefore, the stacked capacitor is increasingly employed following integration of the semiconductor memory device.
However, the stacked capacitor must be more highly formed over a semiconductor substrate in response to refinement of the elements. Following the recent progress of refinement of the elements, it is now becoming difficult to ensure the capacitance required to the capacitor by this method. This also applies to a trench capacitor or a cylindrical capacitor, which is another representative three-dimensional capacitor structure.
Therefore, an attempt of employing a dielectric film consisting of a high dielectric constant material such as BST (barium strontium titanate) as a capacitor dielectric film is made in order to increase the capacitance of the capacitor.
FIG. 28
is a sectional view partially showing a memory cell of a DRAM
150
employing a high dielectric constant material such as BST as a capacitor dielectric film. This semiconductor device
150
comprises a semiconductor substrate
1
, a lower insulating layer
2
, a conductor plug
3
, a barrier metal layer
5
, a lower electrode film
6
, side walls
7
, a dielectric film
8
, an upper electrode film
9
, an upper insulating layer
11
, a,barrier metal layer
60
and a wire
20
. Platinum is employed as the material for the lower electrode film
6
and the upper electrode film
9
, and titanium nitride is employed as the material for the barrier metal layers
5
and
60
. The dielectric film
8
is formed as a BST dielectric film, and the wire
20
is an aluminum wire. The lower insulating layer
2
and the upper insulating layer
11
are formed as interlayer isolation films.
The semiconductor device
150
is characteristically different from any preceding DRAM in that not polycrystalline silicon but a noble metal such as platinum is employed as the material for a capacitor electrode film of a memory cell. In the DRAM preceding the semiconductor device
150
, a silicon oxide film obtained by thermally oxidizing silicon or a silicon nitride film formed by CVD (chemical vapor deposition) is employed as the capacitor dielectric film. Both of silicon oxide and silicon nitride are compounds of silicon, and hence the capacitor dielectric film can be readily formed on a lower electrode film prepared from polycrystalline silicon.
When a dielectric film consisting of a high dielectric constant material such as BST (barium strontium titanate) is formed on a polycrystalline silicon film, however, the electrochemically base polycrystalline silicon film is so readily oxidized that a silicon oxide film is formed on the interface between the dielectric film of BST and the lower electrode film of polycrystalline silicon. This silicon oxide film remarkably reduces electrostatic capacitance of the capacitor due to its low dielectric constant.
In order to prevent this, a noble metal such as electrochemically noble platinum having high oxidation resistance is employed for the upper electrode film
6
and the lower electrode film
9
in the semiconductor device
150
. Further, the conductive barrier metal layers (anti-diffusion films)
5
and
60
are interposed on the interfaces between the upper and lower electrode films
6
and
9
and the conductive materials mainly composed of silicon and aluminum, which are electrically connected with the electrode films
6
and
9
, for preventing mutual diffusion between silicon and platinum and between aluminum and platinum.
In a process of manufacturing the semiconductor device
150
, the upper insulating layer
11
covering the upper electrode film
9
consisting of a noble metal such as platinum must be etched for forming a contact hole
61
and electrically connecting the upper electrode film
9
and the wire
20
with each other through this contact hole
61
. In this etching step, however, it is disadvantageously difficult to precisely control etching conditions so that the etching is stopped when the upper surface of the thinly formed upper electrode film
9
is exposed not to cause over-etching. Further, a re-deposition film
12
consisting of a component of a resist film and platinum is disadvantageously formed around the bottom portion of the contact hole
61
. The re-deposition film
12
consisting of the component of the resist film and platinum, which is chemically stable and adheres to a portion of the inner wall surface of the contact hole
61
around the bottom portion, is hard to remove. The re-deposition film
12
increases contact resistance.
In order to solve the aforementioned problems, it is possible to assume a capacitor structure obtained by forming an etching stopper layer (not shown) on the upper surface of the upper electrode film
9
. When the etching stopper layer is thickly set to a necessary degree in this structure, however, the effective capacitor height is increased. Consequently, an absolute step is disadvantageously increased between a memory cell array having the capacitor and a peripheral circuit having no capacitor. When the material for the upper electrode film
9
is patterned for forming the upper electrode film
9
, further, a composite film of a three-layer structure including the etching stopper layer and the dielectric film
8
must be etched. Consequently, the upper electrode film
9
cannot be readily finely worked.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a semiconductor device capable of preventing over-etching in formation of a contact hole and preventing formation of a re-deposition film without providing an etching stopper layer and a method of manufacturing the same.
A semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate having a main surface, an insulating layer formed on the main surface of the semiconductor substrate, a lower electrode film embedded in the insulating layer, a dielectric film embedded in the insulating layer and covering the lower electrode film, an upper electrode film embedded in the insulating layer and opposed to the lower electrode film th
Okuno Yasutoshi
Tsunemine Yoshikazu
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