Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-28
2002-12-31
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S647000, C438S657000
Reexamination Certificate
active
06500756
ABSTRACT:
FIELD OF THE INVENTION
The present disclosure relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present disclosure relates to a method of forming sub-lithographic spaces between polysilicon lines.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). ICs often include flash memory cells.
Generally, a transistor is covered by a high temperature oxide and an interlevel dielectric to insulate it from subsequently formed metal layers. An aperture or hole is etched through the interlevel dielectric and the high temperature oxide. The hole is filled with a conductive material to provide connections to the transistor, to conductors, or other circuit structures. For example, a contact can extend from the bit line through the interlevel dielectric to the drain of the transistor. In another example, a contact or conductive via can extend through the interlevel dielectric to connect to the gate stack.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), CMOS fabrication processes must scale the dimensions of the transistors. That is, there must be proportional operational characteristics of structural elements in the ultra-small dimensions of a sophisticated transistor.
One problem associated with CMOS scaling involves forming of smaller and smaller apertures or spaces used in a variety of ways during the IC fabrication process. One way to shrink the critical dimension of “space” features, such as holes and trenches, is with the formation of spacers.
According to conventional processes, an aperture is lithographically formed in a hard mask layer above an underlying layer. The aperture is formed by patterning a photoresist layer above an anti-reflective coating (ARC). A spacer material is conformally deposited in the aperture and stripped in an etch back process. The etch-back process leaves spacers adjacent the side walls of the aperture, thereby shrinking the size of the aperture. The underlying layer is processed using the aperture including the spacers.
Heretofore, conventional spacer formation processes requires the removal of the anti-reflective coating (ARC) and the hard mask after processing. This removal process can damage underlying films, such as oxide-nitride-oxide (ONO) films utilized in flash memory cells and other integrated circuits. There are other drawbacks to the conventional process as well.
Thus, there is a need to form integrated circuits using non-conventional lithographic techniques. Further, there is a need to form spaces smaller than achievable through conventional lithographic methods. Even further, there is a need to avoid damaging underlying films during removal of anti-reflective coating (ARC) and hard masks.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of forming spaces between polysilicon lines. The method can include patterning structures having top SiON layers and bottom amorphous carbon layers where the structures are located over a polysilicon layer and are separated by a first width. The method can also include forming amorphous carbon spacers along lateral side walls of the patterned structures, etching apertures into the polysilicon layer not covered by the amorphous carbon spacers and the patterned structures where the apertures in the polysilicon layer have a second width, and ashing away the amorphous carbon spacers and the patterned structures. The second width is less than the first width.
Another exemplary embodiment relates to a method of forming structures having sub-lithographic spacing. The method can include patterning a first stack having a layer of amorphous carbon and a second stack having a layer of amorphous carbon, and forming amorphous carbon spacers along lateral side walls of the first stack and the second stack. The method also includes etching a layer located below the first and second stacks using the first and second stacks and amorphous carbon spacers as a mask to leave at least two features, and removing the first and second stacks and the amorphous carbon spacers. The first stack and the second stack are separated by a first width. The distance between the at least two features is less than the first width.
Another exemplary embodiment relates to a method of forming spaces between polysilicon lines. The method can include patterning SiON on amorphous carbon to form first and second stacks separated by a first width, and depositing and etching amorphous carbon to form spacers along side walls of the first and second stacks. The method also includes etching a polysilicon layer below the first and second stacks using the first and second stacks and spacers as a mask, and ashing away the first and second stack and the spacers.
Other principle features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
REFERENCES:
patent: 6372636 (2002-04-01), Chooi et al.
patent: 2001/0003667 (2001-06-01), Ahn et al.
patent: 2002/0055230 (2002-05-01), Chang
Bell Scott A.
Fisher Philip A.
Nguyen Richard C.
Tabery Cyrus E.
Advanced Micro Devices , Inc.
Foley & Lardner
Gurley Lynne
Niebling John F.
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