Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-22
2002-11-26
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C430S005000, C118S720000
Reexamination Certificate
active
06487711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of analyzing a factor responsible for an error in a wafer pattern and an apparatus for producing a photolithographic mask. More particularly, the present invention relates to a method of analyzing a factor (hereinafter referred to simply as a “factor analysis method”) for detecting an error in a wafer pattern ascribable to a tolerance of mask patterns and an error in a wafer pattern ascribable to another reason while distinguishing between them, as well as an apparatus suitable for producing a mask for use with the factor analysis method.
2. Description of the Background Art
In a process of manufacturing a semiconductor device, a wafer pattern is transferred onto a semiconductor wafer through use of a photolithographic mask (hereinafter referred to simply as a “mask”). A wafer pattern transferred onto a semiconductor wafer includes an error ascribable to a tolerance of mask patterns (hereinafter referred to as a “mask pattern error”) and an error ascribable to a factor other than a mask pattern error, for example, an error in a stepper, a variation in the thickness of a photoresist film, and a variation in resolution.
It is useful to determine a cause for inducing an error in a wafer pattern for promoting the development of a semiconductor device. However, it has been difficult to ascertain a ratio between a mask pattern error and an error ascribable to another reason.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve such a problem and is aimed at providing a factor analysis method for detecting an error in a wafer pattern ascribable to a mask pattern error and an error in a wafer pattern ascribable to another reason while distinguishing between them.
The above objects of the present invention are achieved by a method of analyzing factor responsible for errors in a wafer pattern formed on a semiconductor wafer. In the factor analyzing method, a first mask is placed in a first position within an etching chamber. A mask pattern is formed by etching the first mask. A second mask is placed in a second position within the etching chamber such that an overlap region exists between a portion of the first mask and a portion of the second mask, provided that the first mask is set in the first position. A mask pattern is formed by etching the second mask. A wafer pattern corresponding to a single shot region is formed on the semiconductor wafer by exposing the semiconductor wafer through use of the first mask. A wafer pattern corresponding to a single shot region is formed on the semiconductor wafer by exposing the semiconductor wafer through use of the second mask. Finally, there are detected a dimensional difference ascribable to a difference between mask patterns and a dimensional difference ascribable to another reason while distinguishing the dimensional differences from each other, by comparison between the size of the wafer pattern which is included in an area (first overlap region) within the single shot region formed through use of the first mask and which corresponds to the overlap region and the size of the wafer pattern which is included in an area (second overlap region) within the single shot region formed through the second mask and which corresponds to the overlap region.
The above objects of the present invention are also achieved by an apparatus for producing a mask pattern by etching a photolithographic mask. The apparatus includes an etching chamber for etching a mask pattern. The apparatus also includes a mask table which retains a mask within the etching chamber and can hold the mask at a first position and a second position such that an overlap region exists between a portion of the mask set in the first position and a portion of the mask set in the second position, provided that the masks are set in the first position and the second position simultaneously.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5728592 (1998-03-01), Yania
patent: 6045671 (2000-05-01), Wu
patent: 6054671 (2000-05-01), Wu
patent: 6261964 (2001-07-01), Wu
patent: 6-232034 (1994-08-01), None
patent: 8-241860 (1996-09-01), None
patent: 11-067655 (1999-03-01), None
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
Stevenson André C.
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