Electrical assembly for semiconductor dice

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

Reexamination Certificate

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C439S065000

Reexamination Certificate

active

06410859

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices and more particularly to an improved method for mounting and electrically interconnecting unpackaged semiconductor dice.
BACKGROUND OF THE INVENTION
Microelectronic packages called “multi chip modules” (MCMs) are constructed with unpackaged semiconductor dice. With a multi chip module, a number of dice are attached to a printed circuit board or other mounting substrate and electrically connected to form various circuits and electronic devices.
One reason for the increased use of multi chip modules is increased system performance. In particular, integrated circuits on multi chip modules can be operated with lower resistances and parasitic capacitances. This is largely a result of decreasing the interconnection length between the dice included in the multi chip module. In addition, overall system performance is improved because the input/output ports can be configured to access the whole module, which can be organized to reduce signal delays and access times. The power requirements are also reduced due to a reduction in the driver requirements.
Typically the unpackaged dice are mounted on a circuit board having an interconnect pattern formed using a process such as screen printing. Different techniques are used for mounting the dice to the board and for providing interconnection and termination of the unpackaged dice. One such technique is referred to as “flip chip bonding”. With flip chip bonding, each die is mounted circuit side down, and bond pads on the die are bonded to corresponding connection points on the circuit board. Flip chips are formed similarly to conventional dice but require an additional process step to form solder bumps on the bond pads. Other techniques for mounting the unpackaged dice to the circuit board include wire bonding, tape automated bonding (TAB) and micro-bump bonding.
In general, with each of these methods the full surface area of the dice (i.e., circuit side or back side) occupies a corresponding area on the circuit board. As is apparent this uses a large surface area of the circuit board. It would be desirable to effect an interconnection between the dice and circuit board in which less surface area is required. This would allow a higher packaging density for the dice.
Another important consideration in constructing multi chip modules is the electrical connection between the bond pads of the unpackaged dice and the connection points on the circuit board. It is important that these electrical connections provide a low resistance or ohmic contact. It is also important to minimize the effect of thermal expansion on the electrical connections. For example, if the dice and the circuit board expand by a different amount, stress can develop at the connection points and compromise the connection.
In view of the foregoing, it is an object of the present invention to provide an improved method for mounting and electrically interconnecting unpackaged semiconductor dice to a circuit board.
It is a further object of the present invention to provide an improved method for interconnecting dice in which a high device density and a reliable electrical connection can be achieved.
It is yet another object of the present invention to provide an improved method for interconnecting dice which can be used with conventional semiconductor dice having flat bond pads.
Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method for mounting and electrically interconnecting semiconductor dice on a supporting substrate, such as a printed circuit board, is provided. The method includes forming a plurality of interconnects on a wafer and then singulating the interconnects by saw cutting along streets of the wafer. Each interconnect is adapted to mount a die on edge to the circuit board. In addition, each interconnect establishes an electrical connection between contact locations on the die (e.g., bond pads) and corresponding connection points on the circuit board.
The wafer and interconnects include a substrate formed of a material such as silicon or alumina, having a low thermal coefficient of expansion (TCE) that matches that of a silicon die. Trenches are etched or sawn into the substrate, insulated with an insulating layer, and then filled with a conductive material to form conductive traces. In the case of sawed trenches, the conductive material would not necessarily cover the length of the trench. Each conductive trace includes a contact bump corresponding to a contact location on the die. In addition, each conductive trace includes an edge portion corresponding to a connection point on the circuit board.
Multiple dice and interconnects are subassembled and then mounted to a circuit board to form a stacked array. For mounting the dice and interconnects to the circuit board, each die is mounted face down on an interconnect with the contact locations on the die in electrical contact with the contact bumps on the interconnect. A z-axis anisotropic conductive adhesive can be used to secure each die to its corresponding interconnect and to provide an electrical connection therebetween. The die-interconnect subassemblies are then placed together in a stacked array of dice and interconnects with the interconnects supporting the dice on edge. A z-axis conductive adhesive, is again used to secure the interconnects to the circuit board and to establish an electrical connection therebetween. With this arrangement, the conductive traces formed on the interconnects provide a circuit path between the connection points on the circuit board and the contact locations on the dice.


REFERENCES:
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patent: 5578527 (1996-11-01), Chang et al.
patent: 5661042 (1997-08-01), Fang et al.
patent: 5661901 (1997-09-01), King
patent: 5751554 (1998-05-01), Williams et al.
patent: 0446112 (1991-09-01), None

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