Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2000-05-16
2002-06-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C710S032000
Reexamination Certificate
active
06411121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits and, in particular, to systems and methods for adjusting signal transmission parameters of an integrated circuit.
2. Description of the Related Art
Integrated circuits (IC's) are electrical circuits which incorporate transistors, resistors, capacitors, and other components onto a single semiconductor “chip” in which the components are interconnected to perform a given function. Typical examples of IC's include microprocessors, programmable logic devices (PLDs), electrically erasable programmable memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators, among others. Generally, IC's incorporate chip pads which are configured for enabling electrical interconnection of external electronic components, such as drivers, for example, with internal components, such as receivers, for example.
A driver associated with an IC typically is configured for providing a signal to a chip pad of the IC via a transmission line. The signal then is provided via the chip pad, and possibly by use of additional transmission lines and/or busses, for example, to a receiver component. During transmission of the signal from the driver to the receiver, mismatches between the driver and the various signal transmission media, and between the receiver and the various signal transmission media may produce signal reflections at the driver end and/or the receiver end signal transmission path associated with the chip pad. These signal reflections may propagate along the transmission path and may potentially result in less than desired electrical performance of the chip.
Additionally, mismatches or variations in transmission paths, i.e., variations between transmission paths of various chip pads of an IC, may result in variations of driver/line signal delays received at a bus of the IC. The collective difference between all pad/line delays, known as bus skew, also may potentially result in less than desired electrical performance of the chip.
Heretofore, it is known to attempt to reduce signal reflections and/or adjust bus skew by controlling groups or blocks of chip pads together based on process, voltage, temperature (PVT) information, such as by applying resistor/impedance components to external pins of the chip to alter driver/receiver impedance of a block of chip pads. Thus, by averaging the PVT information of one area of the chip, the block of pads corresponding to that area may be controlled through the use of one set of external pins. Since chip pads, however, may possess defects/flaws and/or impedances that are different from each other (even different from those of other chip pads in the same block of chip pads), it would be beneficial, in some respects, to provide additional external pins to a chip so that each chip pad could be independently altered, such as by applying resistor/impedance components to external pins of each chip pad, as necessary. However, to invoke the use of such additional external pins would require the use of additional circuits and busses, and would require reallocation of chip resources, such as chip space and routing resources, for example, thereby making such resources unavailable for critical signals, such as clocks, for instance.
Therefore, there is a need for devices, systems and methods which address these and other shortcomings of the prior art.
SUMMARY OF THE INVENTION
Briefly described, the present invention generally relates to systems and methods for adjusting signal transmission parameters of an integrated circuit. In a preferred embodiment, the system includes an integrated circuit incorporating a first chip pad, a first receiver, and process, voltage and temperature (PVT) controls. The first chip pad electrically communicates with the first receiver, with the first chip pad and the first receiver forming at least a portion of a first signal transmission path. The PVT controls are configured to adjust driver delay and/or receiver impedance based upon on-chip conditions of the integrated circuit. Additionally, a controller electrically communicates with the first chip pad, with the controller being configured to sample a first signal corresponding to the first chip pad and adjust the first signal so that line delay and/or signal reflections associated with the first signal are modified, thus, improving performance of the integrated circuit.
In another embodiment, the system includes an integrated circuit incorporating a first chip pad, a first receiver, and process, voltage and temperature (PVT) controls. The first chip pad electrically communicates with the first receiver, with the first chip pad and the first receiver forming at least a portion of a first signal transmission path. The PVT controls are configured to adjust driver delay and/or receiver impedance based upon onchip conditions of the integrated circuit. Additionally, means for sampling a first signal corresponding to the first chip pad and adjusting the first signal is provided so that line delay and/or signal reflections associated with the first signal are modified, thus, improving performance of the integrated circuit.
In another embodiment, the present invention may be generally construed as a method for adjusting signals. Briefly stated, the method preferably includes the steps of: sampling at least one of the signals at the chip pad corresponding thereto to detect signal reflections; and adjusting the at least one of the signals at the chip pad so that line delay and/or signal reflections are modified. So provided, performance of the integrated circuit is improved as compared with the performance of the integrated circuit prior to the step of adjusting.
Other features, and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such features, and advantages be included herein within the scope of the present invention, as defined in the appended claims.
REFERENCES:
patent: 6229335 (2001-05-01), Huang et al.
patent: 6239617 (2001-05-01), Guertin et al.
Agilent Technologie,s Inc.
Chang Daniel D.
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