Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-18
2002-02-19
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06348715
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an SOI device in which floating body effect is reduced and performance is thus improved.
2. Discussion of the Related Art
A background art SOI device will be described with reference to the accompanying drawings.
FIG. 1
is a cross-sectional view of a background art SOI device. This background art SOI device, constituting a CMOS transistor, includes a buried oxide film
2
formed on a semiconductor substrate
1
, a p-type semiconductor layer
4
doped with p-type ions and formed on a predetermined area of the buried oxide film
2
, and an n-type semiconductor layer
5
formed on a predetermined area of the buried oxide film
2
and spaced apart from the p-type semiconductor layer
4
. An isolation oxide film
3
is formed to have a higher height than the p-type and n-type semiconductor layers
4
and
5
to isolate the p-type semiconductor layer
4
from the n-type semiconductor layer
5
.
A gate oxide film
6
and a first gate electrode
7
a
are formed on a predetermined area of the p-type semiconductor layer
4
. Source/drain regions
8
a
/
8
b
having an LDD structure are formed in the p-type semiconductor layer
4
at both sides of the first gate electrode
7
a
. Sidewall spacers are formed on the both sides of the first gate electrode
7
a.
A gate oxide film
6
and a second gate electrode
7
b
are formed on a predetermined area of the n-type semiconductor layer
5
. Source/drain regions
9
a
/
9
b
having an LDD structure are formed in the n-type semiconductor layer
5
at both sides of the second gate electrode
7
b
. Sidewall spacers are formed on both sides of the second gate electrode
7
b.
While an NMOS transistor is formed in the p-type semiconductor layer
4
, a PMOS transistor is formed in the n-type semiconductor layer
5
.
An interlayer insulating film
10
is formed to have contact holes on the source/drain regions
8
a
/
8
b
and
9
a
/
9
b
and the first and second gate electrodes
7
a
and
7
b
. Line layers
11
a
,
11
b
,
11
c
,
11
d
,
11
e
, and
11
f
are formed in the contact holes and on the interlayer insulating film
10
adjoining to the contact holes.
As described above, p-type and n-type semiconductor layers
4
and
5
, which serve as channels of the NMOS transistor and PMOS transistor, float in the background art SOI device.
Such a background art SOI device has the following problems. A p-type semiconductor layer and an n-type semiconductor layer, serving as channels of the NMOS and PMOS transistors, are electrically connected, yet float, so that breakdown voltage is reduced and floating body effect is generated so that errors in current-voltage curve are generated. Accordingly the operation characteristic becomes inferior.
SUMMARY OF THE INVENTION
Therefore, the present invention is directed to an SOI device that substantially obviates one or more of aforementioned problems due to limitations and disadvantages of the related art.
An object of the invention is to provide an SOI in which channel regions of NMOS and PMOS transistors are electrically connected to first and second conductivity type semiconductor layers, respectively, having contact pads through first and second conductivity type polysilicon layers, thereby reducing floating body effect and thus improving the operation characteristics.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the SOI device includes a semiconductor substrate; a first buried insulating film formed on the semiconductor substrate; a first conductivity type silicon layer formed on the first buried insulating film; an active region and a first conductivity type semiconductor layer formed to be isolated on predetermined areas of the first conductivity type silicon layer; second buried insulating films formed to be isolated from one another in the first conductivity type silicon layer to connect the first conductivity type semiconductor layer with the active region through the first conductivity type silicon layer; a gate electrode formed on the active region; impurity region formed in the semiconductor substrate at both sides of the gate electrode; and contact pads formed on the first conductivity type silicon layer.
In another aspect of the present invention, a method for fabricating an SOI device includes the steps of forming first insulating films formed in a first semiconductor substrate to be spaced apart by a predetermined distance; forming first insulating layers to expose predetermined areas of the first semiconductor substrate between the first films; forming a first silicon layer on the first semiconductor substrate including the first buried insulating layers; forming a second buried insulating layer on a second semiconductor substrate; bonding the first silicon layer with the second buried insulating layer; polishing the first semiconductor substrate until the first insulating films are exposed to form semiconductor layers of first and second regions; implanting ions into the first silicon layer to form a first conductivity type silicon layer; forming a gate electrode on the semiconductor layer of the first region; implanting ions into the semiconductor layer of the second region to form a second conductivity type semiconductor layer; forming impurity regions in the semiconductor layer of the first region at both sides of the gate electrode; and forming a contact pad in contact with the second conductivity type semiconductor layer and simultaneously line layers in contact with the impurity regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4970175 (1990-11-01), Haisma et al.
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5260233 (1993-11-01), Buti et al.
patent: 5521399 (1996-05-01), Chu et al.
patent: 5528054 (1996-06-01), Ipposhi et al.
patent: 5597739 (1997-01-01), Sumi et al.
patent: 6096581 (2000-08-01), Zhang et al.
Terukazu Ohno et al., International Electron Devices Meeting 1995 (IEDM 95), pp. 627-630.
H.F. Wei et al., International Electron Devices Meeting 1993 (IEDM 93), pp. 739-742.
Chaudhuri Olik
LG Semicon Co. Ltd.
Trinh (Vikki) Hoa B.
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