Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-08
2002-12-31
Pham, Long (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S664000, C438S938000, C257S770000, C257S785000
Reexamination Certificate
active
06500759
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device including a titanium silicide layer and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device in which a fine interconnecting effect is suppressed by avoiding the effect by stress in a titanium silicide layer, and to a method of manufacturing the semiconductor device.
BACKGROUND OF THE INVENTION
Salicide (self aligned silicide) technology is known as a means for speeding-up and high integration of semiconductor devices. This technology is typified by self-adjustably forming metal silicide layers
26
a
and
26
b
on, for example, silicon-containing layers comprising a gate electrode
22
and an impurity region
24
formed on a silicon substrate
20
, in an MOS type semiconductor device, as shown in FIG.
10
. Suppressing the resistance of the metal silicide layers
26
a
and
26
b
is desirable for increasing the speed of the circuit.
However, a problem called a fine interconnecting effect is known to occur when the width of the interconnecting is reduced. The following problems occur in the technology utilizing a titanium silicide layer. Specifically, decreasing the width of the gate electrode and impurity region to increase the degree of integration results in an increase in both the fluctuation of resistance and the average resistance value in titanium silicide layers.
The reason for the fine interconnecting effect is considered to be as follows. There are two types in titanium silicide. One has a high resistance (about 100 &OHgr;·cm) crystal structure (called “C49 structure”), and the other has a low resistance (about 15&OHgr;·cm) crystal structure (called “C54 structure”). The high resistance crystal structure (C49 structure) is formed at a temperature of about 400° C. to 600° C., whereas the low resistance crystal structure (C54 structure) is formed at a higher temperature of about 700° C. to 800° C. However, as the interconnectings become fine, a phase transition from the high resistance crystal structure to the low resistance crystal structure is obstructed, resulting in a higher ratio of the high resistance crystal structure. In addition, fluctuation in the ratio of the low resistance crystal to the high resistance crystal increases as the interconnecting becomes minute. For these reasons, when the interconnecting width of the gate electrode and the like is less than a certain level, for example, less than about 0.35 &mgr;m, the problems of fluctuation in the resistance of titanium silicide layers and an increase in the average value of the resistance become conspicuous.
DISCLOSURE OF INVENTION
An object of the present invention is to provide a semiconductor device in which a fine interconnecting effect is suppressed by avoiding the effect of stress in a titanium silicide layer, and a method of manufacturing the semiconductor device.
A method of manufacturing a semiconductor device of the present invention comprises:
a step of forming a titanium layer on a region which contains a conductive silicon-containing layer;
a step of forming a protective layer having compression stress on the titanium layer; and
a step of forming a titanium silicide layer by reacting silicon in the silicon-containing layer and titanium in the titanium layer by thermal processing.
In this method of manufacturing a semiconductor device, the titanium silicide layer is formed between the silicon-containing layer and the titanium layer by thermal processing on condition that the tensile stress in the titanium layer is weakened by the compression stress of the protective layer. Specifically, it is possible to suppress generation of stress which obstructs a phase transition in the titanium silicide layer by the protective layer having compression stress. This method ensures to obtain titanium silicide in which the phase transition from the high resistance crystal structure (C49 structure) to the low resistance crystal structure (C54 structure) easily occurs.
As a result, the fine interconnecting effect can be suppressed making it possible to obtain a semiconductor device having low resistance and exhibiting only a small fluctuation in the resistance of titanium silicide layers, even if the interconnecting width of a gate electrode and the like is less than a certain level, for example, equal to or less than 0.35 &mgr;m.
In the present invention, the protective layer is formed from a layer having compression stress as a film stress at least under the condition that the protective layer is connected to a silicon substrate in which the silicon-containing layer is formed.
Taking sheet resistance of the titanium silicide layer and the like into consideration, the protective layer may have a compression stress in a range from 1×10
9
Dyne/cm
2
to 2×10
10
Dyne/cm
2
, and more preferably from 7×10
9
Dyne/cm
2
to 2×10
10
Dyne/cm
2
.
In addition, the protective layer may not contain oxygen or may have characteristics which do not allow oxygen to permeate. Because oxygen reacts with titanium and prevents the titanium from becoming the silicide.
For the above reasons, the protective layer may be made from at least one metal selected from tungsten, cobalt, tantalum, and molybdenum.
Examples of the thickness of each layer of the present invention are as follows. The thickness of each layer is appropriately determined according to design criteria and the like. In particular, the thickness of the protective layer is determined taking into account such factors as capability of securing smooth phase transition from the C49 structure to the C54 structure in the titanium silicide layer, and of obtaining a conductive layer which exhibits a small sheet resistance and small fluctuation in the sheet resistance.
The titanium layer may have a thickness of 10 nm to 50 nm.
The protective layer may have a thickness of 1 nm to 40 nm, and preferably 5 nm to 20 nm.
The silicon-containing layer may be at least one of a gate electrode including polycrystalline silicon formed on the silicon substrate and an impurity layer formed on the silicon substrate.
The method of manufacturing a semiconductor device of the present invention comprises following steps (a) to (f):
(a) a step of forming an isolation dielectric layer and a gate insulating layer on a silicon substrate, and forming a gate electrode containing silicon as a main component on the gate insulating layer;
(b) a step of forming a side spacer formed of an insulating layer on a side of the gate electrode;
(c) a step of forming an impurity layer which functions as at least one of a source and a drain by introducing an impurity in the silicon substrate;
(d) a step of forming a titanium layer entirely;
(e) a step of forming a protective layer having compression stress on the titanium layer; and
(f) a step of forming a titanium silicide layer by reacting silicon in the silicon-containing layer and titanium in the titanium layer by thermal processing.
The step (f) may comprise:
a first thermal processing of forming a titanium silicide layer by converting the titanium layer into silicide; and
a second thermal processing for effecting a phase transition of the titanium silicide layer.
The semiconductor device of the present invention may be obtained by the above-described method. Specifically, the semiconductor device comprises:
a silicon substrate;
a silicon-containing layer having conductivity; and
a silicide layer containing titanium silicide as a main component formed on the silicon-containing layer, wherein the silicide layer is formed by forming a titanium layer on the silicon-containing layer, forming a protective layer having compression stress on the titanium layer, and converting titanium layer into silicide by thermal processing.
Preferably, the silicon-containing layer has a width of 0.35 &mgr;m or less, and the silicide layer has a sheet resistance of 5 &OHgr;/cm
2
or less.
REFERENCES:
patent: 4690730 (1987-09-01), Tang et al.
patent: 5811335 (1998-09-01), Santangelo et al.
patent: 5874342 (1999-02-01), Tsai et al.
p
Oliff & Berridg,e PLC
Pham Long
Pham Thanh V
Seiko Epson Corporation
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