Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-13
2002-12-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06499134
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for improving integrated circuit (IC) performance in view of crosstalk and time-of-flight characteristics associated with package-related wiring for the IC.
Advances in IC design and manufacturing technologies have resulted in progressively smaller IC feature sizes, having commensurately lower operating voltages and packed more densely. Also, performance of ICs at increasingly higher frequencies is demanded. As such trends continue, the importance of handling performance-degrading factors such as crosstalk (coupling noise), and of reducing signal propagation times, also referred to as time-of-flight (TOF), becomes greater.
Higher device density on an IC chip, or die, requires correspondingly denser package-related wiring for carrying signals on and off the die, while the higher clock rates associated with higher frequencies require faster signal transition and reduced TOF for signals on and off the die. Thus. the crosstalk and TOF behavior of the package-related wiring for a die affect overall crosstalk and TOF performance.
Package-related wiring on an IC die can be implemented in a number of different forms, but typically includes at least I/O circuits coupled to “nets” or signals that are input or output to a logic design on the die. The I/O circuits receive input signals and drive output signals off the die, via connections to off-die package pads in a package containing the die. The package pads are in turn typically connected, via a card pad in a card including multiple die packages, to other package pads connected via I/O circuits to other logic designs.
As signals that may be input/output to a logic design approach the several hundreds or more and die interface speeds scale upward, the crosstalk and TOF characteristics of the package-related wiring become factors that significantly impact performance. Accordingly, a method for improving chip performance with respect to the crosstalk and TOF characteristics of the package-related wiring is needed.
SUMMARY OF THE INVENTION
A method according to the present invention provides for establishing an assignment of signals to package-related wiring such that the assignment meets desired crosstalk and TOF constraints.
In an embodiment, I/O circuits corresponding to signals that are input/output to a die in a package are selected for assignment to package wiring meeting defined crosstalk and TOF criteria.
In the foregoing embodiment, a software tool according to the invention uses a database including crosstalk and TOF characteristics for the package wiring to identify package wiring meeting crosstalk and TOF constraints specified by a user. The software tool produces a graphic display highlighting components of the package wiring in terms of their crosstalk and TOF characteristics, and allows a user to graphically assign the selected I/O circuits to wiring meeting the required constraints. The assignment of the I/O circuits constitutes part of a definition of a floorplan for the die which will result, when the die is physically fabricated, in package-related wiring corresponding to the assignment of I/O circuits and consequently having the desired crosstalk and TOF characteristics.
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Buffet Patrick H.
Dunn Paul E.
Natonio Joseph
Proctor Robert A.
Yasar Gulsun
Connoly Bove Lodge & Hutz LLP
International Business Machines - Corporation
Levin Naum B
Sabo William D.
Siek Vuthe
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