Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-20
2002-08-13
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S633000, C438S638000, C438S687000, C438S780000
Reexamination Certificate
active
06432811
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits and fabrication methods, and more particularly to the formation of integrated circuits with insulation layers having low dielectric constants.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide.
A consequence of having of patterned conductive material separated by an insulating material, whether the conductive material is on a single level or multiple levels, is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, unnecessary power dissipation, and capacitively coupled signals, also known as cross-talk.
One way to reduce the unwanted capacitance between the interconnects is to increase the distance between them. Increased spacing between interconnect lines has adverse consequences, such as increased area requirements and the corresponding increases in manufacturing costs. Another way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant.
What is needed is a structure providing low parasitic capacitance between patterned conductors, and methods of making such a structure.
SUMMARY OF THE INVENTION
The present invention is a process of forming reinforcement structures from a copper diffusion barrier for use in highly porous dielectric layers of integrated circuits. According to the present invention the process involves forming an electrically non-conductive copper diffusion barrier on a substrate and then patterning the barrier to form reinforcement structures. A highly porous dielectric layer is then formed over the reinforcement structures and subsequently polishing the dielectric layer so that its surface is even with the top surfaces of the reinforcement structures.
REFERENCES:
patent: 5461003 (1995-10-01), Havermann et al.
patent: 6004863 (1999-12-01), Jang
Blakley Sokoloff Taylor & Zafman LLP
Nguyen Ha Tran
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