Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-23
2002-10-08
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S371000, C257S369000, C257S903000, C257S904000, C257S499000
Reexamination Certificate
active
06462385
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having twin wells and a manufacturing method thereof.
2. Description of Related Art
There are a variety of different types of SRAMs, one form of semiconductor memory devices. One type of SRAMs employs CMOS devices. SRAMs using the CMOS have been aggressively developed in recent years since the CMOS has excellent characteristics such as low power consumption. However, the CMOS has a serious drawback in that it exhibits a latch-up phenomenon.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problems as described above. It is another object of the present invention to provide a semiconductor memory device having a construction in which the latch-up phenomenon hardly occurs, and a method for manufacturing the same.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate, a peripheral circuit region and a memory cell region on the principal surface of the semiconductor substrate. The semiconductor memory device has a first well formed in the peripheral circuit region, a first conductivity type second well formed in the memory cell region, a second conductivity type third well formed in the memory cell region and having substantially the same depth as the depth of the second well, and a device element isolator formed in the memory cell region for isolating the device element formed in the second well from the device element formed in the third well. The second and third wells extend to an area under the device element isolator. The second and third wells may be further provided with a first layer having a depth shallower than the first well, and a second layer having the same depth as the first well. The first layer of the second well overlaps the first layer of the third well under the device element isolator. The second layer of the second well and the second layer of the third well are isolated from each other.
The depth of the first layer in the second and third wells formed in the memory cell region may be shallower than the depth of the first well formed in the peripheral circuit region in accordance with one embodiment of the present invention. Accordingly, overlap of the first layers at the boundary between the first layer in the second well and the first layer in the third well under the device element isolator can be diminished. The reasons will be described below. Therefore, in accordance with an embodiment of the present invention, the distance between one well and a source/drain in another well formed adjacent to the one well may be prevented from becoming too short without elongating the length of the device element isolator. Consequently, the embodiment structure prevents an increase in the leak current in a parasitic MOS that triggers the latch-up phenomenon while miniaturizing the semiconductor memory device.
In accordance with one embodiment, the second and third wells may have second layers. Resistance of the second and third wells (substrate resistance) can be lowered by the second layers, while preventing occurrence of the latch-up phenomenon.
In accordance with one embodiment, the second layer in the second well and the second layer in the third well are isolated from each other. If the two layers were to have contact with each other, the overlap between the second well and the third well at their boundary could not be reduced. The reason will also be described below.
In accordance with embodiments of the present invention, the device element isolator includes a LOCOS oxide film, a semi-recess LOCOS oxide film, and a shallow trench (with a depth of about 0.4 to 0.8 &mgr;m) or the like. The term “source/drain” refers to at least one of a source region and a drain region.
The second well has the same depth as the depth of the third well in accordance with one embodiment of the present invention. Therefore, substantially no imbalance in performance between transistors, attributable to the difference between the well depths, occurs in the memory cell region. It is noted that, in this specification, the term “the same depth” is not strictly limited to the same depth but also covers a well depth difference that causes substantially no imbalance in performance between transistors.
Since the second well has the same depth as the third well according to the present invention, the depth of the source/drain in the second well can be adjusted to be the same as the depth of the source/drain in the third well. Therefore, no imbalance in performance among transistors due to different depths of the source/drain is caused.
In accordance with one embodiment of the present invention, the source/drain to be formed in the second and third wells does not become too shallow, compared to the source/drain to be formed in the first well.
The well contact region for fixing the well potential is isolated from the source/drain. The second and third wells extend to a position under the device element isolator. Consequently, the wells can be extended to the well contact region, allowing the second and third wells to be readily connected to the well contact region.
The source/drain of a transistor formed in the first well, the source/drain of a transistor formed in the second well and the source/drain of a transistor formed in the third well preferably have substantially the same depth in accordance with one embodiment of the present invention. As a result, sources/drains of the same conductivity type can be simultaneously formed.
In a preferred embodiment of the present invention, the first, second and third wells are retrograded wells. The retrograded well refers to a well formed by high-energy ion implantation without using a thermal diffusion method.
Each of the first, second and third well as a retrograded well is provided with a layer with a first concentration, a layer with a second concentration, a layer with a third concentration and a layer with a fourth concentration in the order from the top to the bottom. The first layer in the second well and the first layer in the third well are composed of the layers with the first, second and third concentrations. The second layer in the second well and the second layer in the third well are composed of the layers with the fourth concentration. The layer with the first concentration comprises, for example, a channel doped layer for adjusting the threshold voltage V
th
of the transistor. The layer with the second concentration comprises, for example, a punch-through stopper layer for suppressing a short-channel effect of the transistor. The layer with the third concentration comprises, for example, a channel-cut layer for preventing action of a parasitic transistor in a region including the device element isolator. The layer with the fourth concentration comprises, for example, a low resistive layer for decreasing the well resistance.
In accordance with one embodiment of the present invention, a CMOS type cell SRAM is formed in the memory cell region. The CMOS type cell SRAM refers to an SRAM in which the cell is composed of the CMOS.
In a preferred embodiment of the present invention, the length of the device element isolator for dividing adjacent wells in the memory cell region is in the range of about 0.2 &mgr;m to 1.6 &mgr;m. Since the boundary between the second well and the third well is required to be located under the device element isolator, and a positional deviation may occur in patterning the resist, a minimum length to cover the positional deviation is necessary in the device element isolator. This minimum length may preferably be about 0.2 &mgr;m. When the length of the device element isolator is longer than 1.6 &mgr;m, the memory cell size may become too large.
The depth of the first layers in the second and third wells is preferably in the range of about 0.5 &mgr;m to 1.2 &mgr;m in accordance with one embodiment of the present invention. When the depth of the first layer in the second and third wells is less than about
Flynn Nathan J.
Hogan & Hartson LLP
Mondt Johannes
Seiko Epson Corporation
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