Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-07-09
2002-12-03
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S156000, C711S136000
Reexamination Certificate
active
06490665
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 88103372, filed Mar. 5, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer memory management, and more particularly, to a memory-access management method and system which is designed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations.
2. Description of Related Art
In a computer system, a master unit is used to control the access operations, whether read or write, to the primary memory of the computer system. In general, the memory access would be focused on some particular segments rather than all the segments in the primary memory; in other words, some segments would be most often accessed than others. In the design of a memory-access management system, the primary concern is directed to the reduction of overhead and latency.
The SDRAM (Synchronous Dynamic Random-Access Memory) is a new type of memory device. Each SDRAM unit is typically partitioned into four sub-banks, each sub-bank containing a number of pages and only one of which can be opened at the same time. In other words, in each SDRAM unit, at most four pages can be opened at the same time. Conventionally, each sub-bank is associated with one memory control unit for managing the pages in the sub-bank. Therefore, for each SDRAM unit, four memory control units are required. This page management scheme, however, has the following drawbacks.
First, in the case a memory slot is unused or is mounted with an SDRAM unit that contains only two sub-banks, the provision of four memory control units will not be fully utilized, and therefore is cost-ineffective in utilization.
Second, when VC-SDRAM (Virtual Channel SDRAM) is used, since each VC-SDRAM unit can provide 16 channels, the provision of four memory control units will allow only four of the 16 channels to be usable and the other 12 channels to be unused. A solution to this problem is to provide 16 memory control units for each VC-SDRAM unit. However, this solution would require a very large circuit layout area to incorporate all the 16 memory control units, and therefore is quite cost-ineffective. Moreover, the use of 16 memory control units would cause a large delay to the access operation and therefore is unsuitable for use with a high-speed computer system.
There exists, therefore, a need for a new memory-access management method and system which can be used with various types of memory devices, including SDRAM, VC-SDRAM, and EDO DRAM.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a new computer memory-access management method and system, which is designed for use with an SDRAM or the like, for the purpose of increasing the performance of memory access to the SDRAM.
In accordance with the foregoing and other objectives of this invention, a new computer memory-access management method and system is provided.
The memory-page management system of the invention includes a comparison unit, a page-table register unit, a utilization-rate register unit, and a validity-checking unit.
The page-table register unit includes a page table for storing a predefined number of recently accessed memory locations to the memory unit, each stored memory location being stored along with a least-recently-used record indicative of whether the stored memory location is least recently accessed.
The comparison unit is capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit; if hit, the comparison unit generating a hit signal;
The utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and the validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.
The page-table register unit includes: a latch circuit, coupled to the comparison unit, for latching the output signals from the comparison unit indicative of whether the memory location is a hit to the page table; and a selection circuit, coupled to the latch circuit, the utilization-rate register unit, and the validity-checking unit, for selecting one of the stored memory locations in the page table based on the output signals from the latch circuit, the utilization-rate register unit, and the validity-checking unit.
The page table further includes a plurality of validity bits, each being in association with one of the stored memory locations in the page table, with the validity bit indicating whether the associated memory location is valid or invalid. Each validity bit is set and updated by the comparison unit.
Each least-recently-used record is represented by a numerical value in a predefined range of numbers, with the smallest value indicating that the associated memory location has been most recently accessed and the highest value indicating that the associated memory location has been least recently accessed. The least-recently-used record in association with each stored memory location in the page table is set and updated by the utilization-rate register unit.
In the event that the current access request is a miss to the page table, the memory location of the current access request is used to replace the one whose least-recently-used record has the highest value; and before the memory location of the current access request replaces the one whose least-recently-used record has the highest value, the validity-checking unit checks whether the associated validity bit is set to indicate validity; if yes, a restore signal is generated to restore the corresponding memory location to original state.
In accordance with another aspect of the invention, the memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations to the memory unit, each stored memory location including a bank address and a page address, and each stored memory location being stored along with a least-recently-used record and a validity bit, with the least-recently-used record indicative of whether the associated memory location is least recently used and the validity bit indicative of whether the associated memory location is valid or invalid; and each least-recently-used record being represented by a numerical value in a predefined range of numbers, with the smallest value indicating that the associated memory location has been most recently accessed and the highest value indicating that the associated memory location has been least recently accessed. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a bank hit or a page hit to any one of the memory locations stored in the page table in the page-table register unit; the comparison unit generating a bank-hit signal if bank hit and a page-hit signal if page hit. Moreover, a utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit, and in the event of page miss and bank miss to the page table, capable of replacing the one of the stored memory locations in the page table that is least recently accessed with the memory location of the current access request; and a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.
In accordance with another aspect, the invention provides a memory-page
Chen Chia-Hsin
Kao Chih-kuo
Lai Jiin
Anderson Matthew D.
J. C. Patents
Kim Matthew
Via Technologies Inc.
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