Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-23
2002-12-17
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06496964
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for designing a semiconductor device, and more particularly, to a method for designing a semiconductor device operated at different power supply voltages.
In the prior art, two methods have been proposed to design the layout of a semiconductor device having multiple power supply systems. These two methods are described below.
In the first method, information of a power supply line (net list) is generated. Power line patterns are connected to circuit patterns based on the line information to separate power supplies.
In the second method, a library of logic elements is prepared for each type of power supply. Power supply connections are determined based on each library to design a layout that separates power supplies.
However, in the first method, the designer must accurately recognize the power supply terminal of each logic element and know what type of power supply is connected to each logic element to generate the net list of the power supply line. This makes it burdensome to the designer.
Further, in the second embodiment, the number of libraries that have to be prepared increases as the types of power supplies increases. This limits the application of the libraries.
In addition, the information for separating the power supplies is generated only when the logic elements are determined in the first and second methods.
Methods of logic simulation (e.g., delay calculation) and power consumption calculation have also been proposed. These methods (i.e., a third method and a fourth method) are described below.
In the third method, a multiple power supply semiconductor device is assumed to be a single power supply semiconductor device to perform delay calculation and power consumption calculation.
In the fourth method, a functional macro is set for each power supply, and the delay calculation and power consumption calculation is performed for each functional macro.
However, errors in the results of the delay calculation and power consumption calculation are relatively large in the third method. Thus, operational confirmations may not be performed accurately and the estimate of power consumption may not be accurate. As a result, re-designing may become necessary.
The semiconductor device is divided into multiple functional macros in the fourth method. This makes it difficult to inspect the semiconductor device as a whole. Further, the usage of macros decreases the designing efficiency.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method that facilitates the designing of a layout of a semiconductor device operated by multiple power supplies.
To achieve the above object, the present invention provides a method for de signing a semiconductor device having a plurality of logic elements provided with a plurality of power supplies. The method includes giving a power supply type name to each power supply in accordance with the purpose of the power supply in each logic element, associating each logic element with the power supply type name of the power supply that is to be provided to the logic element, forming a power supply group for each power supply, generating specific information of each power supply group associating the power supply type name with supplied voltage, and determining the power supply provided to each logic element by allocating the power supply group, which is associated with the supplied voltage and the power supply type name of the power supply provided to the logic element, to the logic element.
The present invention also provides a computer readable recording medium recording a program for designing a semiconductor device having a plurality of logic elements provided with a plurality of power supplies. The program includes the steps of giving a power supply type name to each power supply in accordance with the purpose of the power supply in each logic element, associating each logic element with the power supply type name of the power supply that is to be provided to the logic element, forming a power supply group for each power supply, generating specific information of each power supply group associating the power supply type name with supplied voltage, and determining the power supply provided to each logic element by allocating the power supply group, which is associated with the supplied voltage and the power supply type name of the power supply provided to the logic element, to the logic element.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 5972740 (1999-10-01), Nakamori
patent: 6086628 (2000-07-01), Dave et al.
patent: 6170079 (2001-01-01), Kato et al.
patent: 6434730 (2002-08-01), Ito et al.
Inui Masuo
Suzuki Kenji
Toki Rieko
Yamamoto Hiroyuki
Yoneda Takashi
Fujitsu Limited
Lam Tuan T.
Nguyen Hiep
Staas & Halsey , LLP
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