Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-04
2002-10-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06463566
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the field of charge integrating devices.
Charge generation is necessary whenever CCD signal processing circuitry must interface with voltage-domain signals. A variety of techniques are well known for generating charge packets from voltages. In all of these, an input diffusion is used to provide a source of electrons and the amount of charge that is collected from this source is controlled by either the source potential or the voltages on an initial set of register gates.
The surface channel fill-and-spill technique, shown diagrammatically in
FIG. 1
, is the most commonly used method of charge generation.
FIG. 1A
is a schematic diagram of a conventional fill-and-spill charge generator circuit
100
, and
FIGS. 1B-1E
are associated potential diagrams for a second, third, fourth and first phase, respectively. In this approach, the input signal v
s
is provided to gate G
2
and a fixed reference level V
r
is placed on G
1
. During the fill phase in
FIG. 1B
, node f
g
is pulsed low and charge is injected into the channel regions underneath G
1
and G
2
. During the spill phase in
FIG. 1C
, f
g
is returned to a high potential so that excess charge from the output well spills back. The spill transition occurs rapidly at first, but then slows considerably as it nears completion. The long time constant associated with this spill transition limits the speed at which the fill-and-spill circuit can be operated. In addition to its limited speed, the fill-and-spill technique has the disadvantages that it provides poor linearity and does not perform accurate sampling.
Charge-domain signals can be used by non-CCD elements in two ways. The first method, referred to as destructive sensing, involves transferring the charge packet onto a receiving element. In this case, the charge packet is consumed by the operation. The second method, referred to as nondestructive sensing, involves creating a separate representation of the charge packet, without altering the original, so that multiple nondestructive operations can be performed on the same charge packet.
A schematic diagram of a conventional nondestructive floating gate amplifier circuit
200
is illustrated in FIG.
2
A.
FIGS. 2B-2E
are associated potential diagrams for a first, second, third and fourth phase, respectively. The circuit includes a sensing gate G
4
within a CCD channel. The sensing gate and the barrier that precedes it are not clocked. In preparation for receiving charge, node v
g
is preset to the intermediate bias level V
h
during the time that the G
4
channel is empty. The precharge is then turned off and v
g
is left floating. During the next phase, a charge packet is transferred underneath G
4
by lowering the voltages on G
1
and G
2
. As charge collects underneath G
4
, it couples through the gate-to-channel capacitance and causes the potential on v
g
to fall. The clocked v
g
waveform is then buffered to form the voltage-domain output v
b
.
This approach to charge sensing has the disadvantage that nonlinearity is introduced by voltage dependence of its various capacitances. It also is not compatible with low voltage operation. because unclocked CCD gates, G
3
and G
4
, reside in the charge transfer path. Finally this circuit provides only a limited signal range before charge collects underneath G
3
and is not sensed by the floating gate.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a charge processing circuit which integrates charge at an output node that is representative of an input charge provided at an input node. The circuit includes a precharge path coupled to the input node, the precharge path operable for setting the potential of the input node to a fixed precharge potential prior to introduction of input charge to the input node. A sensing path is coupled to the input and output nodes which is operable for returning the potential of the input node to the fixed precharge potential subsequent to introduction of input charge to the input node. A feedback element has an input coupled to the sensing path and the precharge path, the feedback element operable for setting said fixed precharge potential.
In accordance with another embodiment of the invention, there is provided a method of integrating charge at an output node of a charge processing circuit that is representative of input charge provided at an input node. The method includes replenishing charge at the input node; draining charge from the input node; stopping the draining of charge from the input node in response to a feedback element detecting when the input node reaches a fixed precharge potential; introducing an input charge on the input node from a source; draining charge from the input node onto the output node; and stopping the draining of charge from the input node in response to a feedback element detecting when the input node reaches the fixed precharge potential.
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patent: 5748235 (1998-05-01), Kondo et al.
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patent: 5969758 (1999-10-01), Sauer et al.
patent: 5982205 (1999-11-01), Vallancourt
patent: 6025935 (2000-02-01), Tseng
patent: 6118482 (2000-09-01), Clark et al.
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patent: 6147551 (2000-11-01), Hong
patent: 6320617 (2001-11-01), Gee et al.
patent: 6366320 (2002-04-01), Nair et al.
“A Distributed Floating-Gate Amplifier in Charge-Coupled Devices” by wen et al., ISSCC 75/ Wednesday, Feb. 12, 1975.
Dinh Paul
Massachusetts Institute of Technology
Samuels , Gauthier & Stevens, LLP
Smith Matthew
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