Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-19
2002-08-06
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S653000, C438S687000, C438S765000, C438S958000
Reexamination Certificate
active
06429117
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices used in integrated circuits, and specifically to a method of creating copper traps during fabrication of semiconductor devices.
BACKGROUND OF THE INVENTION
Without treatment, the dielectric surface is susceptible to copper (Cu) penetration and diffusion. Thus there is potential damage to the device since Cu has a long diffusion length, especially with the number of thermal cycles present in the normal process flow.
U.S. Pat. No. 5,451,542 to Ashby describes a method for passivating compound semiconductor surfaces by photolytically disturbing molecular sulfur vapor with ultraviolet radiation to form reactive sulfur which then reacts with, and passivates, the compound semiconductor surfaces.
U.S. Pat. No. 5,953,628 to Kawaguchi describes a method for forming copper wiring for a semiconductor device within SiO
2
insulating layers. An SiO
2
insulating layer and an intermediate SiO
2
insulating layer are stacked successively. An opening is formed within the intermediate SiO
2
insulating layer and a copper wiring is formed within the opening. The copper wiring is covered with an anti-oxidation layer that is not a transition metal as in conventional semiconductor devices, but is copper sulfide (Cu
x
S where 0<×≦2).
U.S. Pat. No. 5,990,008 to Koyama et al. describes a method of forming high aspect copper structures that permits a heightened degree of copper burying. For example, a fine connecting hole may be formed in a layer insulating film on a silicon substrate. A CVD-TiN barrier film is formed on the etched insulating film as an adhesive film, and a copper film having thickness of 1 &mgr;m is then formed over the TiN adhesive film. The copper film has a high level of purity with an oxygen concentration of 0.5 ppm or lower, and a sulfur concentration of 0.06 ppm or lower. A heat treatment is applied and a copper fine contact hole is formed without voids.
U.S. Pat. No. 5,431,774 to Douglas describes a method of dry etching metals, such as copper, using—acids in an energetic environment such as a plasma, laser, or afterglow reactor, or by using ligands forming volatiles at low temperatures within a pulsed energetic environment.
U.S. Pat. No. 5,821,168 to Jain describes a process for forming a semiconductor device in which an insulating layer is nitrided and then covered by a thin adhesion layer before depositing a composite copper layer. The process does not require a separate diffusion barrier as a portion of the insulating layer (SiO) is converted to form a diffusion barrier film (SiON) by performing a plasma nitriding step.
U.S. Pat. No. 5,831,283 to Batey et al. describes a layer for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to prevent copper penetration and diffusion into the dielectric surface.
Another object of the present invention is to create a copper barrier by strong adhesion with ligand sites binding copper.
A further object of the present invention is to create a polymer ‘virtual’ copper barrier that is highly resistant to thermal cycles due to the stability of the polymers.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.
REFERENCES:
patent: 4965656 (1990-10-01), Koubuchi et al.
patent: 5431774 (1995-07-01), Douglas
patent: 5451542 (1995-09-01), Ashby
patent: 5821168 (1998-10-01), Jain
patent: 5831283 (1998-11-01), Batey et al.
patent: 5953628 (1999-09-01), Kawaguchi
patent: 5990008 (1999-11-01), Koyama et al.
patent: 6001415 (1999-12-01), Nogami et al.
patent: 6294836 (2001-09-01), Paranjpe et al.
patent: 6309982 (2001-10-01), Chooi et al.
Aliyu Yakub
Chooi Simon
Gupta Subhash
Ho Paul Kwok Keung
Roy Sudipto Ranendra
Ackerman Stephen B.
Chartered Semiconductor Manufacturing Ltd.
Elms Richard
Pyonin Adam
Saile George O.
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