Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1999-07-07
2002-06-25
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C710S001000
Reexamination Certificate
active
06412068
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of mass storage systems. In particular, the invention relates to the management of input-output processors and other cards populating a file server for a mass storage system.
2. Description of the Related Art
The storage of large amounts of data in so-called mass storage systems is becoming a common practice. Mass storage systems typically include storage devices coupled to file servers on data networks. As the amount of storage has increased, the number of file servers in networks has grown, and the concept of a storage area network (SAN) has arisen. Storage area networks connect a number of mass storage systems in a communication network which is optimized for storage transactions. The file servers that manage SANs control many storage devices.
Numerous users in a network communicate with the file servers in a mass storage system for access to data. They depend on nearly continuous access to data, excepting scheduled interruptions. Techniques for managing startup of file servers which utilize redundant controllers and storage devices and techniques for monitoring the operational status of file srver components have become increasingly important. These techniques contribute to reliable access to data without unscheduled interruption of user access.
SUMMARY OF THE INVENTION
The present invention provides a card management system architecture for managed startup of a system and for monitoring its operation. Both a method and device particularly suited to carrying out the method are provided.
According to one embodiment of the method, a second controller evaluates the status of power supplies and then powers up a first controller and processors on input-output processors (IOPs). The first controller evaluates the status of individual IOPs and enables additional power and data interfaces.
Additional embodiments involve additional structures and steps. Redundant channels for communications among controllers and IOPs are preferred. In one embodiment, the first bus is implemented as five serial communication lines. Communication between redundant first controllers and between redundant second controllers allows determination of which controllers should be active. Determining which controllers are active may depend on whether the same controllers are in the system as had been in the system during the last proper operation of the system. Enabling a supply of power may depend on whether two or more power supplies are available. Availability of power supplies cooled by fans may depend on whether AC power is available and within appropriate voltage ranges, what the operating temperature is for the power supplies and the speed and status of the cooling fans.
The evaluation of the status of individual IOPs may involve sending messages to particular addresses where IOPs are potentially located and evaluating a response or non response from each particular address. The messages for communication may be in a fixed format. In one preferred embodiment, the fixed format consists of eight fields. The status of the system may be output for display.
The device particularly suited to carrying out the claimed method includes first and second busses, a controller coupled to the first bus, IOPs each including a first processor, a second processor and a bus access switch, and logic for the controller to communicate with the IOPs across the first bus. Additional embodiments of the device add redundant channels for communication across the first bus, which may include five lines for serial communication. The second bus may be a parallel data bit bus, compliant with the peripheral component interconnect (PCI) standard. The IOPs may also include a power control switch which controls power to second processors and other components on IOPs, which is operated in response to messages from the first controller. The first controller may use a fixed message format including eight fields. The first controller may function by sending messages to particular addresses where IOPs are potentially located and then evaluating the responses or non-responses to determine the status of IOPs. The first processors may be able to signal a processor reset or a non-maskable interrupt to the second processors, in response to messages received from the first controller.
In one embodiment of the present invention, the first processors may have an additional power supply which functions without dependance on messages from the first controller. The first processors may each be coupled to a power switch which the first processor operates in response to messages from the first controller, or in the case of the first processor on the first controller, in response to messages from the second controller. The power switch controls the supply of power to certain components of the IOPs, including the second processors and the bus access switch.
In an embodiment of the present invention, there may be redundant first controllers and redundant second controllers. The redundant controllers may communicate and be equipped with logic that enables them to determine which controllers should be active and which should be passive.
REFERENCES:
patent: 5170472 (1992-12-01), Cwiakala et al.
patent: 5272584 (1993-12-01), Austruy et al.
patent: 6085276 (2000-07-01), Van Doren et al.
patent: 6173341 (2001-01-01), Emerson et al.
Field, III Oliver C.
McDermott Craig
Merrell Alan R.
Nolan Shari J.
Panas Michael G.
Dell Products L.P.
Hamilton & Terrile LLP
Heckler Thomas M.
Terrile Stephen A.
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