Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-13
2002-12-17
Crane, Sara (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06496967
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method of placing datapath cells within a datapath macro to minimize signal propagation time and datapath macro area.
Integrated circuits typically include datapath macros. A datapath macro is an arrangement of datapath blocks connected by data buses and control signals. The data buses are generally routed orthogonally to the control signals. Each datapath block contains one or more datapath cells. Each of the datapath cells are connected to one or more of the data buses and to one or more of the control signals. As the size and complexity of the datapath macros and constituent datapath blocks increases, it becomes increasingly difficult for cell placement tools to arrange the datapath cells so that the signal propagation time through the datapath macro and the area of the datapath macro are minimized under complex input constraints imposed on the placement of cells, pins, nets, gaps between cells, and so on.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the problems above as well as other problems by providing a method of datapath cell placement that minimizes signal propagation time and datapath macro area.
In one embodiment, the present invention may be characterized as a method of datapath cell placement that includes the steps of receiving a datapath description of constrained input pins, unconstrained input pins, and output pins for a datapath block; assigning a first corresponding first cell level to a first datapath cell in a data path of a constrained input pin wherein the first corresponding first cell level is representative of a number of intervening datapath cells between the first datapath cell and the constrained input pin; assigning a second corresponding first cell level to a second datapath cell in a data path connecting the first datapath cell to an unconstrained input pin that is substantially identical to the first corresponding first cell level; and assigning a corresponding second cell level to the datapath cell in the data path connecting the first datapath cell to the unconstrained input pin wherein the second cell level is representative of a number of intervening datapath cells between the datapath cell in the data path of the unconstrained input pin and the unconstrained input pin.
REFERENCES:
patent: 6049224 (2000-04-01), Britton et al.
Tetelbaum Alexander
Yu Qiong J.
Crane Sara
Fitch Even Tabin & Flannery
LSI Logic Corporation
LandOfFree
Method of datapath cell placement for an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of datapath cell placement for an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of datapath cell placement for an integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2932539