Power MOS transistor

Details Power MOS transistor Power MOS transistor

2000-09-07

2002-08-20

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257S343000

Reexamination Certificate

active

06437402

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a power MOS transistor for use as a driving stage, such as a pulse generating driver and a switching regulator, for driving a load, and more particularly, to a power MOS transistor comprising a multiplicity of combined MOS transistor cells.
BACKGROUND OF THE INVENTION
A high power MOS transistor is used in pulse generating drive circuits such as a CD driver and a DVD driver and in a switching regulator to drive actuators and motors.
A typical high power MOS transistor includes a multiplicity of MOS transistor cells formed on a semiconductor substrate and connected in parallel with one another.
FIGS. 1A and 1B
show an arrangement of such MOS transistor cells and lead wires therefor in a power MOS transistor.
As shown in
FIG. 1A
, the power MOS transistor cells are formed on a semiconductor substrate having a definite conduction type (which is hereinafter assumed to be p-type). Each MOS transistor cell
11
has a square configuration of 19 &mgr;m×19 &mgr;m for example. Formed at the center of each MOS transistor cell
11
is a source contact
13
to be connected with an n-type source region of the cell. The source contact
13
is surrounded by four drain contacts
14
located at the four corners of the cell, which are connected with respective n-type drain region of the cell.
A meshed gate
12
is formed over the semiconductor substrate via a insulating oxide layer such that the four nodes of each mesh are located on the four sides of the cell, as shown in the figure.
The gate
12
has a p-type layer that underlies the meshes, n-type regions adjacent the drain contacts
14
to serve as drains, and n-type regions adjacent the source contacts
13
to serve as sources. This arrangement can be attained through a self-alignment technique in which gates are used as masks while forming sources and drains by ion injection. Formed on and connected to the back side of the semiconductor substrate are back gate contacts
15
.
Aluminum source leads
16
extend over and across the gate
12
in the horizontal direction as shown in
FIG. 1B
, so that they connect together the source contacts
13
of the MOS transistor cells
11
lying below the source leads
16
. Also, aluminum drain leads
17
extend over and across the gate
12
in the horizontal direction as shown in the figure, so that they connect together the drain contacts
14
of the respective MOS transistor cells
11
lying below the drain leads
17
.
Since all the gates
12
of the MOS transistor cells
11
are connected together, they have the same electric potential. Similarly, all the aluminum source leads
16
are connected together to have the same electric potential, and so are the aluminum drain leads
17
to have the same potential. Of course all the back gate contacts
15
of the MOS transistor cells
11
are connected together to have the same electric potential.
These MOS transistor cells
11
are formed on the same monolithic semiconductor count 2000 in total in a rectangular matrix of 40 by 50 cells for example to constitute a giant power MOS transistor.
FIG. 2
shows an arrangement of such numerous MOS transistor cells connected to form a conventional power MOS transistor
20
as mentioned above.
In
FIG. 2
, an assembly or rows and columns of a multiplicity of MOS transistor cells form a power MOS block B. The matrix shaped gates
22
derived from the power MOS block B are connected to the gate leads
221
extending around the block B. The gate leads
221
are provided for connection with the internal circuits of the power MOS transistor
20
. The gate leads
221
may be made of polysilicon since they do not require a large current capacity.
Aluminum source leads
26
are derived from the power MOS block B to the left of the block for connection with the aluminum source extension leads
261
, which are connected with a common source pad
262
. These aluminum source leads
26
, aluminum source extension leads
261
and source pad
262
are formed from the same aluminum layer so that they are connected together. The aluminum drain leads
27
are derived from the power MOS block B to the right of the block B for connection with the aluminum drain extension leads
271
, which are connected to a common drain pad
272
. These aluminum drain leads
27
, aluminum drain extension leads
271
and drain pad
272
are formed from the same aluminum layer so that they are connected together.
The power MOS transistor
20
thus formed of many MOS transistor cells has a large capacity and performs switching operations in just the same manner as an ordinary MOS transistor.
In such a conventional power MOS transistor
20
consisting of many combined MOS transistor cells, aluminum source leads
26
and aluminum drain leads
27
are extended out of the block B and connected to an aluminum source extension lead
261
and to an aluminum drain extension lead
271
, respectively, which extension leads
261
and
2
.
71
are in turn connected to a source pad
262
and a drain pad
272
, respectively.
The aluminum source extension leads
261
and the aluminum drain extension leads
271
must have sufficiently large conduction areas so that the power MOS transistor
20
has a desired low ON-state resistance, allowing a required current density for the power MOS transistor
20
. The dimensions of the aluminum source extension leads
261
and the aluminum drain extension leads
271
are determined to meet the requirement.
Consequently, it is difficult for a conventional power MOS transistor
20
to harmonize two requirements that the ON-state resistance of a power MOS transistor
20
be reduced for an improvement of the current density by enlarging the leads, and that the chip size be minimized for economy of cost.
SUMMARY OF THE INVENTION
In accordance with the invention, a power MOS transistor including a multiplicity of MOS transistor cells formed on a semiconductor substrate and connected in parallel. The power MOS transistor includes a first power MOS block and a second power MOS block. The first power MOS block includes a first half of the MOS transistor cells and is equipped with a first set of source leads and a first set of drain leads for connecting in parallel the first half of the MOS transistor cells. The second power MOS block includes a second half of the MOS transistor cells and is equipped with a second set of source leads and a second set of drain leads for connecting in parallel the second half of the MOS transistor cells.
A planar source extension lead is formed on the upper surface of the first power MOS block. A planar drain extension lead is formed on the upper surface of the second power MOS block. The first set of source leads of the first power MOS block and the second set of source leads of the second power MOS block are connected with the planar source extension lead, while the first set of drain leads of the first power MOS block and the second set of drain leads of the second power MOS block are connected with the planar drain extension lead. The first power MOS block and the second power MOS block are disposed beside each other.
The first and the second sets of source leads and the first and the second sets of drain leads of the first and the second power MOS blocks are formed to extend in one direction. The first set of source leads of the first power MOS block are connected to the planar source extension lead at one side of the planar source extension lead, and the second set of source leads of the second power MOS block are connected to another side of the planar source extension lead. The first set of drain leads of the first power MOS block are connected to the planar drain extension lead at one side of the planar drain extension lead, and the second set of drain leads of the second power MOS block are connected to another side of the planar drain extension lead.
The first set of source leads of the first power MOS block protrude along one direction of the first power MOS block and form a first source protruding section. The first set of drain leads protr

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