Semiconductor device manufacturing: process – Forming schottky junction – Compound semiconductor
Reexamination Certificate
2000-08-22
2002-06-11
Smith, Mathew S. (Department: 2825)
Semiconductor device manufacturing: process
Forming schottky junction
Compound semiconductor
C438S574000, C438S578000
Reexamination Certificate
active
06403456
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a method for forming a gate structure with a contact area wider than a base area.
BACKGROUND OF THE INVENTION
Historically, gate structures having a base area with a width that is smaller than the gate contact area (e.g., T-gate and Y-gate structures) have been advantageous in several technologies. For example, MESFET, HEMT (variant of gallium arsenide field effect transistor technology) mainly used in satellite broadcasting receivers, high speed logic circuits and power modules have employed gate structures with bases smaller than the contact area. These types of devices are required in field effect transistors for operation in ultra-high frequency ranges. The advantage of employing a gate structure with a shorter gate length is that the channel of the gate is reduced resulting in an increased in speed and a decrease in power consumption. Reducing the distance over which the gate's field effect control of the electrons in the channel reduces the parasitic resistances and capacitances that limit device speed. A shorter gate length decreases the transmit time for carriers in the channel but also increases the series resistance of the gate electrode itself, slowing down the device and degrading the frequency characteristics of the device. Providing a gate structure with a smaller base than its contact area decreases the gate channel while providing a low gate series resistance due to the wider contact area and, thus, improving the devices drive current capability and performance.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Recent advances in CMOS transistor architecture make use of the T-gate or Y-gate structures where the polysilicon gate electrode is narrowed in the gate regions and wider on top of the gate. This is due to the ever increasing demand for scaling down semiconductor devices and scaling down power consumption requirements. However, the current methods for forming a gate structure with a contact region wider than its base suffers from shortcomings. For example, the etch process which narrows the base of the structure are known to be difficult to control especially with local pattern density. This can lead to variation in the gate width and asymmetric implant profiles. Another problem is related to manufacturing controls. The “re-entrant” or overhung profile prevents direct measurement of the critical gate length.
In view of the above, there is an unmet need for improvements in methodologies for formation of gate structures with contact areas that are wider than the base area.
SUMMARY OF THE INVENTION
One aspect of the invention relates to a method for fabricating a T-gate structure. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. A photoresist layer is formed over the second sacrificial layer. An opening is formed in the photoresist layer. An opening is then formed in the second sacrificial layer beneath the opening in the photoresist layer. The opening is then expanded in the photoresist layer to expose portions of the top surface of the second sacrificial layer around the opening in the second sacrificial layer. The opening is extended in the second sacrificial layer through the first sacrificial layer and the opening is expanded in the second sacrificial layer to form a T-shaped opening in the first and second sacrificial layers. The photoresist layer is removed and the T-shaped opening is filled with a conductive material.
Another aspect of the present invention relates to another method for fabricating a T-gate structure. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer and a single sacrificial layer over the protection layer. A photoresist layer is formed over the single sacrificial layer. An opening is formed in the photoresist layer exposing a portion of the single sacrificial layer. The exposed portion of the single sacrificial layer is etched to extend the opening partially into the single sacrificial layer. The opening in the single sacrificial layer extends from a top surface of the single sacrificial layer to a first depth. The opening is expanded in the photoresist layer to expose portions of the top surface of the single sacrificial layer around the opening in the single sacrificial layer. The expanded opening in the photoresist layer is etched to extend the opening of the single sacrificial layer through the single sacrificial layer to the protection layer and the opening is expanded in the single sacrificial layer at the first depth to form a T-shaped opening in the single sacrificial layer. The photoresist layer is removed and the T-shaped opening filled with a conductive material.
Yet another aspect of the present invention provides for yet another method for fabricating a T-gate structure. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. A photoresist layer is formed over the second sacrificial layer. An opening is etched in the photoresist layer exposing a portion of the second sacrificial layer. The etching is highly selective to the photoresist layer over the underlying second sacrificial layer. The exposed portion of the second sacrificial layer is etched to extend the opening into the second sacrificial layer. The etching is highly selective to the second sacrificial layer over the photoresist layer and the underlying first sacrificial layer. The opening is expanded in the photoresist layer to expose portions of the top surface of the second sacrificial layer around the opening in the second sacrificial layer using an oxygen plasma etch. The opening of the second sacrificial layer is etched through the first sacrificial layer and the opening in the second sacrificial layer expanded to form a T-shaped opening in the first and second sacrificial layers. The etching is highly selective to the second sacrificial layer and the first sacrificial layer over the photoresist layer and the underlying protection layer. The photoresist layer is removed and the T-shaped opening filled with a conduct
Lyons Christopher F.
Plat Marina
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Malsawma Lex H
Smith Mathew S.
LandOfFree
T or T/Y gate formation using trim etch processing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with T or T/Y gate formation using trim etch processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and T or T/Y gate formation using trim etch processing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2931301