Methods of forming trench isolation regions having...

Details Methods of forming trench isolation regions having... Methods of forming trench isolation regions having...

2000-01-07

2002-10-08

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000

Reexamination Certificate

active

06461937

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit device fabrication methods and, more particularly, to methods of forming field oxide isolation regions in semiconductor substrates.
BACKGROUND OF THE INVENTION
Improved active device isolation techniques are desired in order to facilitate ongoing attempts to increase integration density in integrated circuit devices by designing devices having reduced unit cell size. Conventional device isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) techniques, for example. Such device isolation techniques are disclosed in U.S. Pat. Nos. 5,677,234, 5,750,433, 5,753,562, 5,837,595, 5,858,842 and 5,885,883.
But, such techniques as LOCOS may not be appropriate for state-of-the-art high integration devices because they typically result in the formation of isolation regions having bird's beak oxide extensions which typically consume relatively large amounts of surface area. To address this and other problems, STI techniques have been developed. One such technique is illustrated by
FIGS. 30A-30E
. In particular,
FIG. 30A
illustrates the steps of forming a pad oxide layer
3
, a pad nitride layer
4
, a high temperature oxide (HTO) layer
5
and an anti-reflective layer
6
on a semiconductor substrate
2
. A photoresist layer
10
is then patterned on the anti-reflective layer
6
. A trench mask
8
is then formed by performing an etching step using the patterned photoresist layer
10
as an etching mask. As illustrated by
FIG. 30B
, another etching step is then performed to define a trench
12
in the substrate
2
, using the trench mask
8
as a etching mask. During the etching step, the anti-reflective layer
6
may also be removed.
Referring now to
FIG. 30C
, a thermal oxide layer
14
is then formed in the trench to remove etching damage. A trench isolation layer comprising an undoped silicate glass (USG) layer
15
and a PE-TEOS oxide layer
16
(for reducing stress in the USG layer), is then formed to fill the trench
12
. As illustrated by
FIG. 30D
, a planarization step (e.g., CMP) is then performed, using the pad nitride layer
4
as an etch stop layer. Then, as illustrated by
FIG. 30E
, the pad nitride layer
4
and pad oxide layer
3
are sequentially removed to define a trench isolation region
18
Unfortunately, because the substrate
2
may have a substantially different coefficient of thermal expansion than the USG layer
15
in the trench
12
, substantial stresses may develop in the substrate
2
during back-end processing. These stresses may adversely influence the device characteristics of active devices formed in active regions extending adjacent the trench isolation region
18
. The subsequent formation of an oxide layer on the active regions (e.g., gate oxide layers) may also act to increase the degree of stress in the substrate
2
, due to volume expansion in the trench isolation region
18
. Grain dislocation defects and pits may also be generated at the bottom corners and sidewalls of the trench in response to the volume expansion. Such defects may lead to increases in junction leakage currents in adjacent active devices, and decreases in reliability and yield.
To inhibit the formation of grain dislocations and pits at the corners and sidewalls of the trench isolation regions during back end processing steps, silicon nitride layers have been used in trench isolation regions to provide stress relief. Such silicon nitride stress relief layers are described in U.S. Pat. No. 5,447,884 to Fahey et al., entitled “Shallow Trench Isolation With Thin Nitride Liner”.
FIG. 1
is also a graph that illustrates the reduction in junction leakage currents that may occur when silicon nitride stress relief layers (SiN) are provided in trench isolation regions. Here, the leakage currents were measured as the drain “off” currents for MOSFETs formed adjacent a trench isolation region. These currents were measured by grounding the gate electrode, the source region and the substrate and applying a voltage of 3.3 volts to the drain region of the MOSFET. In
FIG. 1
, the symbols -□- designate the leakage currents when silicon nitride stress relief layers are not used and the symbols -∘- designate the leakage currents when silicon nitride stress relief layers are provided.
Referring now to
FIGS. 2-4
, a conventional method of forming a trench isolation region having a silicon nitride stress-relief layer therein will be described. In particular,
FIG. 2
illustrates the steps of forming a pad oxide layer
53
on a surface of a semiconductor substrate
51
and then forming a silicon nitride masking layer
55
on the pad oxide layer. A conventional etching step is then performed to etch a trench in the substrate
51
, using the masking layer
53
as an etching mask. The sidewalls and bottom of the trench are then thermally oxidized to define a sidewall insulating layer
56
. A blanket silicon nitride stress-relief layer
57
is then deposited onto the sidewall insulating layer
56
and onto a sidewall and upper surface of the masking layer
55
. A relatively thick blanket trench isolation layer
59
is then deposited onto the stress-relief layer
57
. The trench isolation layer
59
may comprise silicon dioxide and may be formed by a chemical vapor deposition (CVD) technique. A planarization step is then performed to etch back the trench isolation layer
59
and the stress-relief layer
57
, using the masking layer
53
as a planarization stop layer. This planarization step may be performed by chemically-mechanically polishing (CMP) the trench isolation layer
59
and the stress-relief layer
57
until the masking layer
55
is exposed.
Referring now to
FIG. 3
, an isotropic wet etching step is then performed to selectively and preferably completely remove the masking layer
55
and expose the pad oxide layer
53
. This etching step may be performed using an etchant that selectively etches silicon nitride at much higher rates than silicon dioxide (e.g., phosphoric acid H
3
PO
4
). However, during this etching step, the silicon nitride stress-relief layer
57
may also be etched in the vertical direction “V” and in the lateral direction “L” as the silicon nitride masking layer
55
is consumed. As illustrated, this vertical and lateral etching may cause the stress-relief layer
57
to become recessed to a level below the surface of the substrate
51
. As will be understood by those skilled in the art, these recesses (or “dents” ) may adversely effect the isolation characteristics of the resulting trench isolation region if steps are not taken to fill the recesses with additional stress-relief material during subsequent processing steps. For example, the presence of the recesses may negatively impact the refresh characteristics of devices such as dynamic random access memory (DRAM) devices and may increase an inverse narrow width effect (INWE) in field effect transistors. Increases in INWE may also increase threshold voltage levels and cause a parasitic hump phenomenon to develop in the transistor's I-V characteristics. The presence of the recesses may also increase the likelihood that conductive bridges will be formed between adjacent active regions if the recesses become filled with electrically conductive material during subsequent process steps. In particular, if the degree of recession is significant enough, the recesses illustrated by region A in
FIG. 4
may remain even after a selective etching step is performed to etch-back the pad oxide layer
53
and the trench isolation layer
59
and define a final trench isolation region having a planarized trench isolation layer
59
′ and silicon nitride stress-relief layer
57
′.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of forming trench isolation regions and trench isolation regions formed thereby.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming trench isolation regi

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