Patterning method in semiconductor device fabricating process

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Reexamination Certificate

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C430S314000, C430S317000, C438S094000, C438S748000

Reexamination Certificate

active

06376155

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a patterning method in a semiconductor device fabricating process, and more specifically to a method for patterning a film on a semiconductor substrate by a wet etching.
2. Description of Related Art
In a semiconductor device fabricating process, a Novorak resin is conventionally used in a step for forming in an insulating film a contact hole for interconnecting an upper level conducting film and a lower level conducting film. However, in order to realize a high throughput and a high level of microfabrication, it is necessary to use a chemical amplification resist in patterning the insulating film.
One example of the patterning method using the chemical amplification resist is disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-07-120934 (an English abstract of JP-A-07-120934 is available and the content of the English abstract is incorporated by reference in its entirety into this application). This prior art example proposes a chemical amplification resist developing method for preventing a so-called “T top” which is generated at the time of patterning a conductor by using a positive photoresist. It was discovered that a cause for generation of the “T top” is a hard-dissolving layer formed on a surface of a selectively exposed positive chemical amplification resist layer. When the selectively exposed positive chemical amplification resist layer is developed, first, the development is carried out by using a first developing solution including an activator for elevating affinity to the chemical amplification resist material, until the hard-dissolving layer is dissolved, and thereafter, the development is continued by using a second developing solution including no activator and therefore having a highly selective dissolving property until the development is completed. Thus, the positive chemical amplification resist pattern having a desired shape can be formed. If an underlying conductor layer (a material layer to be etched) is patterned by using the positive chemical amplification resist pattern thus formed, there is obtained a conductor layer patterned to have a desired line width with no difference between the line width of the positive chemical amplification resist pattern (width of “T top”) and the line width of an actually etched conductor layer, namely with no so-called conversion difference.
However, when an interconnecting contact hole is formed in an insulating film, which is different from the case of patterning the conductor, It was found out that the following problem has been encountered. If the lithography using the chemical amplification resist is carried out without modifying a process which was carried out using the Novorak resist in the prior art, the shape of an opening formed in the chemical amplification resist layer has deformed before a step of forming a metal film on a patterned insulating film by means of a CVD (chemical vapor deposition) process or a sputtering. As a result, a desired contact hole could not formed in the insulating film. Under this condition, a metal film cannot be formed in the inside of the contact hole as desired, with the result that a satisfactory electrical interconnection cannot be obtained between an upper level conducting layer and a lower level conducting layer.
A cause for the deformation of the chemical amplification resist layer is considered to be that the insulating film is wet-etched using the chemical amplification resist layer as a mask. As described in detail in Paragraph Nos. 0006 and 0007 of the above referred JP-A-07-120934, the chemical amplification resist is a high-resolution, high-sensitivity resist utilizing a catalytic reaction of acid generated in a portion selectively exposed by an exposure light source, and on the other hand, a wet etching liquid used for patterning the insulating film is a strong acid. Therefore, if the chemical amplification resist is brought into contact with the wet etching liquid, the acid catalytic reaction is easy to occur at a contact surface. As a result, the opening pattern formed in the chemical amplification resist layer by the lithography step becomes deformed in the wet etching step succeeding to the lithography step.
In particular, in the case that an insulating layer is formed in two layers for planarization and an upper level insulating film is wet-etched and succeedingly a lower level insulating film is dry-etched, when a baking is conducted after the wet-etching, diffusion of acid is promoted by a heat of the baking, so that a heavy deformation of the pattern occurs, with the result that the opening formed in the chemical amplification resist layer is often filled up. In this condition, a contact hole is not formed in the lower level insulating film of the double-layer insulating film, so that the upper level conducting film and the lower level conducting film cannot be interconnected.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a patterning method using a chemical amplification resist as a mask, which has overcome the above mentioned defect of the prior art semiconductor device fabricating process.
According to the present invention, in a semiconductor device fabricating process, there is provided a patterning method including the steps of forming a chemical amplification resist layer on a film formed on a semiconductor substrate, patterning the chemical amplification resist layer, and wet-etching the film formed on the semiconductor substrate using the patterned chemical amplification resist layer as a mask, wherein before the wet-etching is carried out, a surface treatment is conducted for the patterned chemical amplification resist layer to elevate a wet-etching-resistance of the patterned chemical amplification resist layer.
The surface treatment for elevating the wet-etching-resistance of the patterned chemical amplification resist layer is, for example, to form, on a surface of the patterned chemical amplification resist layer, a protection film which is insoluble or hard-dissolving to a wet etching liquid, or to treat a surface of the patterned chemical amplification resist layer with a strong alkali liquid, or to expose a surface of the patterned chemical amplification resist layer to plasma, or to irradiate, onto a surface of the patterned chemical amplification resist layer, a radiation different from a radiation of an exposure radiation source used for patterning the chemical amplification resist layer.
As mentioned above, when an insulating film formed on a semiconductor substrate is wet-etched using a patterned chemical amplification resist layer as a mask, after a protecting film insoluble or hard-dissolving to a wet-etching liquid is previously formed at a surface of the patterned chemical amplification resist layer, to elevate a wet-etching-resistance of the patterned chemical amplification resist layer, the wet-etching is actually carried out. Thus, the above mentioned pattern deformation of the patterned chemical amplification resist layer caused by the wet etching is prevented so that an opening pattern of a desired shape is formed in the insulating film formed on the semiconductor substrate. Here, “insoluble to a wet-etching liquid” means a nature which is almost never dissolved by the wet-etching liquid, and “hard-dissolving to a wet-etching liquid” means a nature which is difficult to be dissolved by the wet-etching liquid. In the present invention, it is sufficient if the protecting film is not completely dissolved during a period of time in which the wet etching is carried out, since the chemical amplification resist layer is protected from the wet etching liquid.


REFERENCES:
patent: 6242160 (2001-06-01), Fukuzawa et al.
patent: 0 195 315 (1986-03-01), None
patent: 1096507 (1966-06-01), None
patent: 1 225 754 (1967-06-01), None
patent: 1 422 698 (1973-04-01), None
patent: 2 221 767 (1990-02-01), None
patent: 2-156244 (1990-06-01), None
patent: 5-181281 (1993-07-01), None
patent: 6-556

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