CPLD scalable and array architecture

Details CPLD scalable and array architecture CPLD scalable and array architecture

2001-02-15

2002-08-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S040000, C326S041000

Reexamination Certificate

active

06437598

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
This invention relates to an AND array architecture that enables efficient allocation of logic resources under varying functional requirements.
2. Related Art
Programmable logic devices (PLDs) are user configurable integrated circuits (ICs) that implement digital logic functions. One type of PLD, a programmable logic array (PLA) includes a combinatorial, two-level AND-OR structure that can be programmed to implement sum-of-products logic expressions.
FIG. 1
a
shows a conventional PLA
100
comprising an AND array
101
and an OR array
140
. AND array
101
comprises pterm generators
120
a
-
120
h,
each of which comprises one of a plurality of logic input lines Ia-Ih, and one of AND gates
110
a
-
110
h.
Note that each of logic input lines Ia-Ih actually represents a set of logic input lines, but is depicted as a single line in
FIG. 1
a
for clarity. While eight individual pterm generators are depicted in
FIG. 1
a,
any number could be used in an actual PLD AND array. AND array
101
is coupled to receive input signals d
1
-d
8
on a plurality of PLD input lines
130
, which are formed perpendicular to logic input lines Ia-Ih, thereby creating a grid formation. The PLD input lines and logic input lines are programmably interconnected, wherein electrical connections can be defined at any of the intersections in the grid. The electrical connections can be one-time programmable (e.g., fusible link or antifuse technology), or reprogrammable (e.g., SRAM-based configuration). In
FIG. 1
a,
an “X” is shown at each intersection at which an electrical connection is present. This programmed interconnect matrix therefore routes input signals d
1
-d
8
among pterm generators
120
a
-
120
h
according to the desired function of PLA
100
. Pterm generators
120
a
-
120
h
perform logical AND operations on incoming signals d
1
-d
8
using AND gates
110
a
-
110
h,
respectively, and provide product terms Pa-Ph, respectively, to OR array
120
.
OR array
140
comprises an OR gate
141
coupled to receive pterms Pa-Pd, and an OR gate
142
coupled to receive pterms Pe-Ph. OR gates
141
and
142
perform logical OR operations on their respective pterms, thereby producing the sum-of-products expressions X and Y, respectively. Note that although two OR gates are shown in
FIG. 1
a,
any number of OR gates with any number of inputs could be included in an actual PLD OR array.
OR array
140
further comprises a return line
143
, which allows the output of OR gate
142
to be connected to an input terminal of OR gate
141
. As shown in
FIG. 1
a,
return line
143
is connected to the output of OR gate
142
and ground through an NMOS pass transistor
144
and a PMOS pass transistor
145
, respectively. One of pass transistors
144
and
145
is conducting, and the other is nonconducting, in response to a control signal CONTROL. When control signal CONTROL is in a logic LOW state, return line
143
is connected to ground, and does not affect the operation of OR gate
141
. However, when an OR operation must be performed on a quantity of pterms that exceed the number of input terminals of OR gate
141
(four, in this case, since one input terminal must be dedicated to return line
143
), pass transistor
144
is turned on by a logic HIGH control signal CONTROL. As shown in
FIG. 1
a,
AND array
101
has been programmed to perform the following logical operations:
AND gate
Logic Operation
110a
Pa = d
1
. d
2
110b
Pb = d
3
. d
4
110c
Pc = d
5
. d
6
110d
Pd
= —
110e
Pe = d
7
. d
8
110f
Pf = d
1
. d
4
110g
Pg = d
5
. d
8
110h
Ph = —
Because OR gate
141
only has five input terminals, it cannot perform a logical OR operation on more that number of output pterms from AND array
101
, as would be required for the following PLD operation:
X=d
1
·d
2
+d
3
·d
4
+d
5
·d
6
+d
7
·d
8
+d
1
·d
4
+d
5
·d
8
  [1]
To enable such an operation, OR gate
141
must “borrow” some logic from OR gate
142
. This logic sharing is performed through return line
143
. In other words, OR gate
142
performs the operation:
Y=d
7
·d
8
+d
1
·d
4
+d
5
·d
8
  [2]
This result is then coupled, through return line
143
, to an input of OR gate
141
, which then performs the logical operation:
 
X=d
1
·d
2
+d
3
·d
4
+d
5
·d
6
+(
d
7
·d
8
+d
1
·d
4
+d
5
·d
8
)  [3]
which, by the transitive property resolves to the desired operation [1], i.e.,:
X=d
1
·d
2
+d
3
·d
4
+d
5
·d
6
+d
7
·d
8
+d
1
·d
4
+d
5
·d
8
This “logic sharing” technique, while enabling the implementation of more complex logical functions than would otherwise be possible, leads to substantial inefficiency in the use of the logic resources in a PLD. Because one of the input terminals of each OR gate must be dedicated to the return line from another OR gate, that logic is wasted when the return line is not used. In addition, the “looping” of output signals from one OR gate to the input of another OR gate undesirably decreases the speed of the PLD, due to the serial nature of the operation.
As the borrowed logic (i.e., the number of adjacent OR gates that must be coupled to the input terminals of the original OR gate) increases, this looping delay also increases. This inefficiency can be significantly magnified in a large-scale, or complex PLD (CPLD) that is configured to perform a complex logical operation.
Inefficient use of logic resources in a conventional PLD also arises within the individual pterm generators. Because each pterm generator
120
includes a single AND gate with several input terminals, simple logical AND operations (e.g., a two variable AND operation) result in non-use of all the logic associated with the other AND inputs.
FIG. 1
b
illustrates a more detailed diagram of pterm generator
120
a,
including logic input lines Ia
1
-Ia
8
(logic input line Ia in
FIG. 1
a
) coupled to the input terminals of AND gate
110
a.
PLD input lines
130
are formed perpendicular to logic input lines Ia
1
-Ia
8
in a grid formation with programmable interconnections at the intersections of these two sets of lines, thereby enabling input signals d
1
-d
8
to be selectively provided to AND gate
110
a.
An “X” at a particular grid intersection indicates the presence of a conductive link.
Because AND gate
110
a
includes a large number of logic input lines Ia, it is sometimes referred to as a “wide AND gate.” Typical PLAs use wide AND gates to simplify the AND array layout. Consequently, implementation of simple functions in such PLDs wastes much of the available AND logic. For example, as depicted in
FIG. 1
b,
pterm generator
120
a
is configured to perform the following operation:
Pa=d
1
·d
2
  [4]
As shown in
FIG. 1
b
, this function can be implemented by programming logic input lines Ia
1
and Ia
2
to receive input signals d
1
and d
2
. The remaining logic input lines Ia
3
-Ia
8
and their associated logic within wide AND gate
110
a
are not necessary to implement two-term AND function [4]. At the same time, because it is integrated in wide AND gate
110
a,
this unused logic cannot be shared with any other functions being programmed into the overall PLD. Therefore, the implementation of simple AND functions in conventional PLDs is extremely wasteful.
Accordingly, it is desirable to provide an architecture that maximizes the utilization of the available logic in a PLD without adversely affecting PLD performance.
SUMMARY OF THE INVENTION
The present invention provides a “scalable pterm generator” that beneficially enhances the logic-handling capability of an IC. Scalable pterm generators can be used in place of conventional pterm generators in the AND array of a PLA to improve the programmability and utility of the PLA. A scalable pterm generator comprises a selective logic circuit that includes both the wide AND l

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