Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-08-29
2002-12-31
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S238000, C438S710000, C438S782000, C257S634000
Reexamination Certificate
active
06500740
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to fabrication of semiconductor devices such as integrated circuits.
BACKGROUND OF THE INVENTION
As semiconductor devices become smaller, methods for precisely controlling the distribution of dopants within them become increasingly important. Critical semiconductor devices, such as field effect transistors, are in large part defined by precise patterns of different dopants in semiconductor substrates. Changes in those patterns due to unwanted migration can deteriorate the operation and, indeed, the operability of such devices. As a consequence substantial efforts have been made to control the distribution of dopants. The fabrication of complementary metal oxide semiconductor integrated circuits (CMOS circuits) is illustrative.
A variety of applications utilize CMOS integrated circuits. Many CMOS integrated circuits contain a dual-gate structure, illustrated in part by FIG.
1
. Typically, formation of a dual-gate structure begins by forming a gate dielectric region
108
over a silicon substrate
100
having an n-doped region
102
and a p-doped region
104
, separated (isolated) by a field oxide
106
. (A dielectric material is an electrically insulating material, i.e., a material having a resistivity of about
10
6
ohm-cm or greater.) A polysilicon region
110
is typically deposited over the gate dielectric
108
and field dielectric
106
. The portion of the polysilicon
110
overlying the n-doped region
102
is provided with a p-type dopant such as boron or BF
2
, and the portion of the polysilicon
110
overlying the p-doped region
104
is provided with an n-type dopant such as phosphorus or arsenic. Such dual-gate CMOS configurations typically contain a refractory metal silicide layer
112
(or other metal layer) over the doped polysilicon, the refractory metal silicide acting to lower resistance in the gate structure and thereby improve device and circuit performance.
However, n-type and p-type dopants tend to diffuse more readily in refractory metal suicides than in polysilicon. Dopants thus tend to diffuse, for example, from a region of the polysilicon
110
overlying doped silicon region
102
into the silicide layer
112
, laterally in the silicide layer
112
, and then back into the polysilicon
110
at a region overlying the oppositely-doped region
104
. Thus, n-type dopants move into a p-doped polysilicon region and vice versa. The phenomenon is referred to herein as cross-doping. Diffusion of these cross-dopants into the area of the polysilicon adjacent to the underlying gate dielectric causes undesirable shifts in threshold voltage, an important parameter in CMOS design and operation. Moreover, the problem of cross-doping is becoming more severe as the industry moves toward smaller CMOS devices, e.g., moving towards 0.18 &mgr;m length devices, and even more significantly toward 0.12 &mgr;m and lower. The smaller the devices, the larger the effect of cross-dopants on properties such as threshold voltage, and the closer the devices, the less distance the dopants have to laterally travel to interfere with adjacent devices.
Problems are also created by the distribution of dopants in the implanted regions of the polysilicon
110
. Advantageously, the concentration of the implanted, electrically active dopants in the final device should be as high as possible throughout the entire polysilicon layer and, in particular, near the underlying gate dielectric
108
. Typically, however, after the implantation, the majority of dopants lie close to the top of the polysilicon
110
, and an anneal is used to diffuse the dopants toward the gate dielectric
108
. However, the anneal time and temperature required to diffuse the dopants across this distance will often undesirably allow diffusion of some of the dopants laterally within the polysilicon
110
into an oppositely-doped region of the polysilicon
110
, causing cross-doping. This lateral diffusion within the polysilicon
110
is a problem regardless of whether a silicide layer is present. This mechanism of cross-doping is particularly problematic where half the distance between the active regions of adjacent devices becomes comparable to the thickness of the doped regions of the polysilicon
110
. In addition, the use of thinner gate dielectric layers improves device: performance, but only where a relatively large concentration of dopants, advantageously about 10
20
dopants/cm
3
or greater, is located adjacent to the gate dielectric (resulting in what is known in the art as low poly-depletion). If sufficient dopants are not located adjacent to the dielectric layer, the use of a thinner gate dielectric will at best only marginally improve device performance.
It is also possible for dopant distribution to cause problems when forming a refractory metal silicide by a salicide process. In a typical salicide process, a refractory metal is deposited after formation of a polysilicon gate structure, a source and drain, and silicon dioxide or silicon nitride spacers. The device is heated to react the metal with the exposed silicon, thereby forming a refractory metal silicide. Due to a low level of bonding between the refractory metal and the spacers, the silicide typically does not form on the spacers and the unreacted metal can be etched away, leading to what is conventionally known as self-alignment of the silicide structure. Growth of the gate silicide layer in such a salicide process is detrimentally affected if too many dopants, or dopant-based precipitates, are located in the top region of the polysilicon gate structure, where the gate silicide is formed. In addition, because the polysilicon region is typically thicker when using a salicide process, the dopant diffusion distance to the gate dielectric is often increased, thereby allowing encroachment of the underlying channel region that often leads to shorts in the device.
Applicant's copending U.S. patent application Ser. No. 08/902,044 describes a process for device fabrication which reduces the problems of cross-doping and undesirable concentration profiles. However an even greater reduction of these problems would be advantageous. The present invention achieves such reduction.
SUMMARY OF THE INVENTION
In accordance with the invention, a silicon gate field effect device is provided with improved control over the distribution of dopants by forming thin buried layer of oxide within the silicon gate. In essence, a silicon gate device is fabricated by the steps of forming a gate dielectric on a silicon substrate and forming a first layer of the silicon gate (amorphous or polycrystalline) on the dielectric. A thin layer of oxide is formed on the first gate layer, and a second silicon gate layer is formed on the oxide, producing a silicon gate containing a thin buried oxide layer. Dopants are then implanted through the second gate layer and the buried oxide, and the device is finished in a conventional manner. The buried oxide layer, acting as a sieve, maintains high dopant concentration near the interface between the gate and minimizes dopant outdiffusion through the gate.
REFERENCES:
patent: 5275961 (1994-01-01), Smayling et al.
patent: 5548159 (1996-08-01), Jeng
patent: 6096591 (2000-08-01), Gardner et al.
patent: 6214748 (2001-04-01), Kobayashi et al.
Agere Systems Inc.
Elms Richard
Lowenstein & Sandler PC
Luu Pho M.
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