Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1999-06-30
2002-04-23
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S400000, C713S600000
Reexamination Certificate
active
06378082
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to signaling. In particular, the invention relates to strobe signaling.
2. Description of Related Art
Advanced processors usually are developed as an improvement from previous generations. To maintain downward compatibility, newer processors tend to maintain the same features in the older models while incorporating additional features. However, when there is a significant upgrade, maintaining compatibility with existing supporting circuits and/or specifications is a difficult task.
For example, the Accelerated Graphics Port (AGP) is an advanced graphics interface that allows high performance graphics to be generated in a personal computer (PC) platform. The AGP physical interface is optimized for a point to point topology using either 1.5 volt or 3.3 volt signaling. The baseline performance level utilizes a 66 MHz clock to provide a peak bandwidth of 266 megabytes per second (MB/s). The AGP includes two options for higher performance levels.
The first option provides a peak bandwidth of 533 MB/s. This mode uses a double-clocked data technique to transfer twice the data per each AGP clock. This AGP mode, referred to as the 2X transfer mode, or 2X mode, requires additional interface timing strobes and different signal timings from the baseline 1X mode.
The second option provides a peak bandwidth of up to 1066 MB/s. This mode uses a quad-clocked data transfer technique to transfer four times the data per each 66 MHz clock. This mode, referred to as 4X transfer mode, requires differential interface timing strobes and different signal timings from the 66 MHz baseline and the 2X mode AGP requirements.
The 1X and 2X modes can operate at both the 1.5 V and 3.3 V signaling level following the AGP 1.0 specifications. The 4X mode, however, is restricted to the 1.5 V signaling level, following the Accelerated Graphics Port Interface Specification Revision 2.0 published by Intel Corporation dated May 4, 1998 (“AGP 2.0 Specification”) because of signal integrity limitations. Accelerated Graphics Port Interface Specification Revision 1.0 published by Intel Corporation dated Jul. 31, 1996 (“AGP 1.0 Specification”) the strobe input stage is sensed differentially with respect to the analog input reference bias which is nominally set at 0.4. Vddq for a 3.3 V AGP environment. The AGP 2.0 specification introduces the strobe complement signal and hence requires the strobe input stage to be fully differential sensing as opposed to with respect to a reference.
It is desirable to have a physical interface that can accommodate both the 2X and 4X transfer modes. Traditional methods use multiple differential amplifiers with all possible input combinations followed by tristable output stages. This approach is costly from a design perspective because it uses expensive die real estate.
Therefore there is a need in the technology to provide a simple and efficient method to implement a multi-mode strobe signaling to accommodate multiple operational modes of advanced processors.
SUMMARY
The present invention relates to a method and apparatus to generate first and second strobe signals to receive data on an interface port of a processor operating in first and second modes at first and second voltage levels, respectively. The second voltage level is higher than the first voltage level. Briefly, the apparatus comprises a selector provides first and second selected signals from a plurality of signals which corresponds to the first and second modes. The selector operates at the second voltage level. The apparatus further comprises a signal generator that is coupled to the selector to generate the first and second strobe signals from the first and second selected signals.
REFERENCES:
patent: 5951688 (1999-09-01), Moyer et al.
patent: 6092212 (2000-07-01), Muljono et al.
Johnston Robert J.
Rajappa Srinivasan T.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Kenneth S.
LandOfFree
Generating strobe signals at different voltage level modes... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Generating strobe signals at different voltage level modes..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating strobe signals at different voltage level modes... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2928052