Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-07-22
2002-08-20
Hudspeth, David (Department: 2651)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S103000, C711S133000
Reexamination Certificate
active
06438665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is a memory system which includes at least one array of memory cells (e.g., flash memory cells) and circuitry which compares new data to be written to a set of the cells with data already stored in a corresponding set of the cells and writes the new data to the array only if the new data is not identical to the previously stored data, and a computer system which includes such a memory system, and method performed by such a computer system. In preferred embodiments, the memory system is designed to emulate a magnetic disk drive.
2. Description of Related Art
It is conventional to implement a memory system as an integrated circuit including an array of flash memory cells and circuitry for independently erasing selected blocks of the cells.
FIG. 1
is a simplified block diagram of such an integrated circuit (flash memory chip
103
). An integrated flash memory chip such as memory chip
103
of
FIG. 1
(or a memory system including such a memory chip) can be modified in accordance with the present invention to avoid unnecessary writes of data to sectors of flash memory array circuit
16
.
Flash memory array circuit
16
of memory chip
103
comprises rows and columns of nonvolatile flash memory cells. Memory chip
103
also includes I/O pins DQ
0
-DQ
15
(for asserting output data to an external device or receiving input data from an external device), input buffer circuits
122
,
122
A, and
122
B, output buffer circuits
128
,
128
A, and
128
B, address buffer
17
for receiving address bits A
0
through A
17
from an external device, row decoder circuit (X address decoder)
12
, column multiplexer circuit (Y multiplexer)
14
, and control unit
29
(also denoted herein as “controller”
29
).
Each of the cells (storage locations) of memory array circuit
16
is indexed by a row index (an “X” index determined by decoder circuit
12
) and a column index (a “Y” index determined by Y decoder circuit
13
of circuit
14
). Each column of cells of memory array
16
comprises “n” memory cells, each cell implemented by a floating-gate N-channel transistor. The drains of all transistors of a column are connected to a bitline, and the gate of each of the transistors is connected to a different wordline, and the sources of the transistors are held at a source potential (which is usually ground potential for the chip during a read or programming operation). Each memory cell is a nonvolatile memory cell since the transistor of each cell has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of the N-channel transistors) depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored “semipermanently” in the corresponding cell. In cases in which each of the N-channel transistors is a flash memory device, the charge stored on the floating gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner).
The individual memory cells (not depicted) are addressed by eighteen address bits (A
0
-A
17
), with nine bits being used by X decoder circuit
12
to select the row of array
16
in which the target cell (or cells) is (or are) located and the remaining nine bits being used by Y decoder circuit
13
(of Y-multiplexer
14
) to select the appropriate column (or columns) of array
16
. Typically, a set of eight or sixteen target cells (or
256
target cells) in a single row of the array are selected by a single set of eighteen address bits A
0
-A
17
, with Y decoder circuit
13
determining the column addresses of such cells in response to a nine-bit subset of the set of address bits. In response to the other nine address bits A
0
-A
17
, X decoder circuit
12
determines a row address which selects one cell in the selected column.
In a normal operating mode, chip
103
executes a write operation as follows. Address buffer
17
asserts appropriate ones of address bits A
0
-A
17
to circuit
14
and decoder circuit
12
. In response to these address bits, circuit
14
determines a column address (which selects one of the columns of memory cells of array
16
), and circuit
12
determines a row address (which selects one cell in the selected column). In response to a write command supplied from controller
29
, a signal (indicative of data) present at the output of input buffer
122
,
122
A, and/or
122
B is asserted through circuit
14
to the cell of array
16
determined by the row and column address (e.g., to the drain of such cell). During such write operation, output buffers
128
,
128
A, and
128
B are disabled.
In the normal operating mode, chip
103
executes a read operation as follows. Address buffer
17
asserts appropriate ones of address bits A
0
-A
17
to circuit
14
and address decoder circuit
12
. In response to these address bits, circuit
14
asserts a column address to memory array
16
(which selects one of the columns of memory cells), and circuit
12
asserts a row address to memory array
16
(which selects one cell in the selected column). In response to a read command supplied from control unit
29
, a current signal indicative of a data value stored in the cell of array
16
(a “data signal”) determined by the row and column address is supplied from the drain of the selected cell through the bitline of the selected cell and then through circuit
14
to sense amplifier circuitry
33
. This data signal is processed in amplifier circuitry
33
, buffered in output buffers
128
,
128
A, and/or
128
B, and finally asserted at pins DQ
0
-DQ
15
. During such read operation, input buffers
122
,
122
A, and
122
B are disabled.
Chip
103
also includes a pad which receives a high voltage V
pp
from an external device, and a switch
121
connected to this pad. During some steps of a typical erase or program sequence (in which the cells of array
16
are erased or programmed), control unit
29
sends a control signal to switch
121
to cause switch
121
to close and thereby assert the high voltage V
pp
to various components of the chip including X decoder
12
. Voltage V
pp
is higher (typically V
pp
=12 volts) than the normal operating mode supply voltage (typically V
cc
=5 volts or V
cc
=5.5 volts) for the MOS transistors of chip
103
.
When reading a selected cell of array
16
, if the cell is in an erased state, the cell will conduct a first current which is converted to a first voltage in sense amplifier circuitry
33
. If the cell is in a programmed state, it will conduct a second current which is converted to a second voltage in sense amplifier circuitry
33
. Sense amplifier circuitry
33
determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary value of 0 or 1, respectively) by comparing the voltage indicative of the cell state to a reference voltage. The outcome of this comparison is an output which is either high or low (corresponding to a digital value of one or zero) which sense amplifier circuitry
33
sends to output buffers
128
and
128
B (and through multiplexer
124
to output buffer
128
A). One or more of the output buffers in turn asserts a corresponding data signal to corresponding ones of pins DQ
0
-DQ
15
(from which it can be accessed by an external device).
It is important during a write operation to provide the wordline of the selected cell with the proper voltage and the drain of the selected cell with the appropriate voltage level (the voltage determined by the output of each input buffer, asserted through latch/multiplexer
130
to circuit
14
), in order to successfully write data to the cell without damaging the cell.
Internal state machine
120
of control unit
29
of chip
103
controls detailed operations of chip
103
such as the various individual steps necessary for carrying out programming, reading and erasing operations. State machine
120
thus f
Hudspeth David
Schwegman Lundberg Woessner & Kluth P.A.
Tzeng Fred F.
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