Ferroelectric non-volatile memory cell integrated in a...

Details Ferroelectric non-volatile memory cell integrated in a... Ferroelectric non-volatile memory cell integrated in a...

2000-04-28

2002-04-02

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06366488

ABSTRACT:

TECHNICAL FIELD
This invention relates to a ferroelectric non-volatile memory cell, and, more specifically, the invention relates to ferroelectric non-volatile memory cells that are used in a serial configuration, and that have a stacked-type structure that includes a MOS device connected in parallel to a ferroelectric capacitor.
BACKGROUND OF THE INVENTION
Semiconductor integrated ferroelectric electronic non-volatile memory devices comprise a plurality of ferroelectric non-volatile memory cells organized into a matrix, that is, laid into rows or wordlines and columns or bitlines.
Each ferroelectric non-volatile memory cell comprises a MOS transistor and a ferroelectric capacitor.
Conventionally, the processes for fabricating these memory cells includes, once the MOS transistor is integrated into a semiconductor substrate, forming an insulating layer over the entire chip surface.
The ferroelectric capacitor is then formed on top of this insulating layer. This capacitor has conventionally a lower electrode of metal disposed on the insulating layer.
A layer of ferroelectric material covers the lower electrode, and an upper electrode of metal is disposed on the ferroelectric layer.
Ferroelectric cells can be classed basically according to two configurations, namely a strapped or a stacked configuration.
In the former instance, the capacitor is formed outside the active area of the transistor and is connected to the latter by a metal interconnection between a conduction electrode of the transistor and one electrode of the ferroelectric capacitor.
In the latter instance, the ferroelectric capacitor is formed in the active area of the transistor and connected to the latter by a buried contact connecting a conduction electrode of the transistor to the lower electrode of the ferroelectric capacitor.
In this “stacked” configuration, the dimensions of the ferroelectric capacitor are material to a cell area optimization, since this is the configuration that is regarded most appropriate to fill the demands for integration of new CMOS technologies.
However, including special metallizations for the connections between adjacent cells in the same column BL in the matrix increases the size of the memory matrix, and requires process steps otherwise unnecessary.
SUMMARY OF THE INVENTION
Embodiments of the invention provide ferroelectric non-volatile memory cells with such constructional and functional features as to allow improved integration to CMOS devices and overcome the drawbacks with which prior memory cells are still beset.
Presented is a device that includes a semiconductor substrate having a ferroelectric non-volatile memory cell which includes a MOS transistor and a ferroelectric capacitor. The ferroelectric capacitor has electrodes connected directly between the conduction terminals of the MOS transistor. The upper electrode of the ferroelectric capacitor is formed above the second conduction terminals of two adjacent MOS transistor and connected electrically thereto, and is arranged to extend over the ferroelectric material to at least partially overlap the lower electrode. Also presented is a non-volatile memory matrix that includes a plurality of the ferroelectric memory cells that are organized into rows and columns, as well as methods for forming both the memory cells and the memory matrix.
The features and advantages of the structure of a memory cell according to the invention will be apparent from the following description of an embodiment thereof depicting memory cells of the ferroelectric type being arranged in a stacked type of structure and used in a serial configuration, and the ensuing description will make reference to this application field for convenience of illustration only.


REFERENCES:
patent: 5903492 (1999-05-01), Takashima

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