Test structure and methodology for characterizing ion...

Details Test structure and methodology for characterizing ion... Test structure and methodology for characterizing ion...

1999-08-17

2002-08-06

Chaudhuri, Olik (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C438S018000

Reexamination Certificate

active

06429452

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a test structure for characterizing integrated circuit ion implantation processes.
2. Description of the Related Art
High yields are essential to the profitable manufacture of integrated circuits. Inspection technologies that detect fatal manufacturing defects immediately after critical processing is accordingly a very valuable tool in assuring that such manufacture will be economically successful.
A wafer fabrication process typically forms multiple integrated circuits upon each of several silicon wafers processed simultaneously. As the integrated circuits formed on a given silicon wafer are identical copies of a given product, the silicon wafer is sometimes referred to as a product wafer. An individual integrated circuit is also called a “chip” or a “die”. Following wafer fabrication, the die are subjected to functional testing, then separated. Fully functional die are typically packaged and sold as individual units.
In general, the yield associated with a product wafer manufactured using a particular wafer fabrication process depends upon: 1) the number of steps in the wafer fabrication process, 2) the number of defects introduced during each processing step, and 3) the vulnerability of the features formed during a given processing step to the defects introduced during the processing step. Semiconductor chip manufacturing has many sources of defects that impact yield. As used herein chip yield is the measure of total available die minus those lost to systematic (process technology) defects and those lost to random (tool and environmental) defects. A defect is simply a flaw caused by an imperfect manufacturing process. Only some of the defects associated with a given step are “critical” defects, or defects which prevent an integrated circuit containing the defect from performing its intended function. Random defects are of primary concern to many manufacturers of semiconductor devices. Within the category of random defects, two types of defects may occur, visual defects and non-visual defects. Visual defects may be detected during manufacturing with optical and laser based methods. In many cases, if proper electrically sensitive circuits are created, they may also be found with electrical testing. When found they may be identified and corrective actions are typically taken to reduce or eliminate the defects.
Non-visual defects, on the other hand, may be difficult to identify during manufacturing by visual inspection technology (optical or laser). In addition, many non-visual defects may occur during processing steps which do not directly lead to conductive features, making them difficult to identify by electrical testing. One of the most common sources of non-visual defects is the presence of particles on the wafer during ion implantation.
During a typical ion implantation sequence, a photoresist layer is placed over a semiconductor substrate and patterned such that only the areas which are to be implanted are exposed. After patterning of the photoresist is completed, the wafer typically goes into an ion implantation apparatus. The ion implantation apparatus will implant ions into the semiconductor substrate, as depicted in FIG.
1
. Typically, individual transistor gate structures
100
may mask portions of the semiconductor substrate
120
such that the ions are hindered from entering the channel region
130
of the transistor. The ion implantation may be used to form source and drain regions
150
in the semiconductor substrate.
During the transfer of the wafer to the ion implantation apparatus, and while the wafer resides in the ion implantation apparatus, particles may be introduced onto the surface of the wafer. Particles may be present in the ambient air, introduced by processing personnel, suspended in liquids and gases used during processing, or generated by processing equipment. In general, the vulnerability of a particular feature to a given defect is inversely proportional to the physical dimensions of the feature. Thus the smaller the physical dimensions of a feature being formed, the greater the likelihood that a particle of a given size will cause a critical defect. Referring to
FIG. 2
, these particles
160
may block or hinder implantation into portions
170
of the semiconductor substrate
120
. After ion implantation is completed, the wafer is typically subjected to a photoresist strip. During this photoresist strip, any defects which may have been on the upper surface of the wafer will be removed. This process may lead to optically invisible areas in which there is no implant. Additionally, impacts of highly accelerated particles can loosen and break portions of the patterned photoresist. Since the photoresist layer is later removed, these non-visible defects may also be present.
It would therefore be beneficial to develop a method for characterizing the ion implantation procedures and equipment used in integrated circuit fabrication. In particular, it would be advantageous to have the capacity to test for implant shielding due to the presence of particulate contamination. Accurate information on possible particulate contamination would be useful in minimizing or eliminating implant-related defects in integrated circuits fabricated using the processes being tested and supportive the Yield Prediction estimating methodologies.
SUMMARY OF THE INVENTION
The problems outlined above may be solved by a test structure, and the technique for forming and using the test structure, for characterizing defects produced during an ion implantation processes. A layer of a material which may be rendered etch selective depending on the presence or absence of implanted atoms is deposited upon a conductive layer. The etch selective material may, in one embodiment, be rendered etch selective by implanting atoms into the material. The faster etching portions of the etch selective material may be removed, leaving portions of the etch selective material behind. The position of these remaining portions of the etch selective material may be used to approximately determine the location of the defect.
In one embodiment, the process involves the formation of a dielectric material upon a semiconductor substrate. The dielectric material is subjected to an ion implantation process. The ion implantation typically causes the etch rate of the dielectric material to change. In one embodiment, the etch rate of the dielectric material increases when subjected to an ion implantation process. Any particles which are present on the test structure, however, may partially or completely block the ion implantation into the dielectric material, causing portions of the dielectric material to have different etch rates. After ion implantation, the dielectric material is removed. The ion implanted portions of the dielectric layer undergo, in one embodiment, rapid removal, while the partially or completely blocked portions of the dielectric layer are removed more slowly. The etch rate may then be controlled such that only the ion implanted portions of the dielectric material are removed. This leaves portions of dielectric material on the test structure proximate the position of particles which were present during the ion implantation. In this manner, the non-visual defects produced during an ion implantation may be more readily identified.
In an embodiment, a test structure is formed upon a semiconductor substrate. A first dielectric layer is formed upon the upper surface of the semiconductor substrate. A polysilicon layer is then formed upon the first dielectric layer. The polysilicon layer may be patterned into a meandering line which covers a portion of the semiconductor substrate. After pattering of the polysilicon layer, a second dielectric layer is formed upon the polysilicon layer and the first dielectric layer.
The second dielectric layer may be subjected to an ion implantation process. When silicon dioxide or silicon nitride are used as the second dielectric m

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