Semiconductor memory device enabling reduction of test time...

Details Semiconductor memory device enabling reduction of test time... Semiconductor memory device enabling reduction of test time...

2001-07-09

2002-08-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189080, C365S230060

Reexamination Certificate

active

06430097

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device such as a dynamic random access memory (DRAM) wherein it is possible to inspect contact defects between memory cells in a short period time.
2. Description of the Background Art
FIG. 18
is a block diagram showing a schematic configuration of a semiconductor memory device
502
according to a prior art.
Referring to
FIG. 18
, the semiconductor memory device
502
includes a memory cell array
14
having a plurality of memory cells arranged in rows and columns, an address buffer
5
which receives address signals A
0
to A
12
and outputs an internal row address X and an internal column address Y, and a control signal input buffer
6
which captures control signals /OE, /RAS, /CAS and /WE and outputs internal control signals INTZRAS, INTZCAS and INTZWE.
The memory cell array
14
includes memory cells MC arranged in rows and columns, a plurality of word lines WL provided to correspond to the rows of memory cells MC and bit line pairs BLP provided in correspondence with the columns of the memory cells MC. In
FIG. 18
, one memory cell MC, one word line WL and one bit line pair BLP are shown in an exemplary manner.
The semiconductor memory device
502
further includes a control circuit
8
which receives an internal address signal from the address buffer
5
and receives the internal control signals INTZRAS, INTZCAS and INTZWE from the control signal input buffer
6
so as to output a control signal to each block.
The control circuit
8
includes a circuit which receives the internal control signals, INTZRAS, INTZCAS and INTZWE, and outputs a signal S
0
, which activates the sense amplifier, and an equalizing signal BLEQ, which activates the equalizing circuit of the sense amplifier band.
The semiconductor memory device
502
further includes a row decoder
510
which decodes the row address signal X given from the address buffer
5
. The row decoder
510
includes a word driver for driving the addressed row (word line) inside of the memory cell array
14
into the selected condition.
The semiconductor memory device
502
further includes a column decoder
12
which decodes the internal column address Y given from the address buffer
5
so as to generate a column selection signal and a sense amplifier band
516
wherein a plurality of sense amplifiers, which carry out detection and amplification of data of memory cells MC connected to the selected row in the memory cell array
14
, are arranged.
The semiconductor memory device
502
further includes an input buffer
22
which receives writing data from the outside and generates internal writing data, a writing driver which amplifies the internal writing data from the input buffer
22
and transmits them to the selected memory cell, a preamplifier which amplifies the data read out from the selected memory cell and an output buffer
20
which further carries out buffer processing on the data from this preamplifier and outputs them to the outside.
In
FIG. 18
, the preamplifier and the writing driver are shown as one block, the block
18
.
FIG. 19
is a circuit diagram showing the configuration of the row decoder
510
in FIG.
18
.
Referring to
FIG. 19
, the row decoder
510
includes a pre-decoder
532
, which pre-decodes the lowest two bits in the row address, a pre-decoder
536
, which decodes the rest except for the lowest two bits in the row address, and a main decoder
38
, which selects a word line in accordance with the outputs of the pre-decoders
532
and
536
.
The pre-decoder
532
receives signals RA
0
and RA
1
, which correspond to the lowest two bits of the row address, and signals ZRA
0
and ZRA
1
, which are, respectively, complementary to the signals RA
0
and RA
1
. The pre-decoder
536
receives the signals RA
2
to RA
12
, which correspond to the row address except for the lowest two bits, and the signals ZRA
2
to ZRA
12
, which are, respectively, complementary to the signals RA
2
to RA
12
.
The pre-decoder
532
includes a NAND circuit
540
which receives the signals ZRA
0
and ZRA
1
, an inverter
542
which inverts by receiving the output of the NAND circuit
540
and outputs a pre-decode signal X
0
, a NAND circuit
544
which receives the signals RA
0
and ZRA
1
, and an inverter
546
which inverts by receiving the output of the NAND circuit
544
and outputs a pre-decode signal X
1
.
The pre-decoder
532
further includes a NAND circuit
548
which receives signals ZRA
0
and RA
1
, an inverter
550
which inverts by receiving the output of the NAND circuit
548
and outputs a pre-decode signal X
2
, a NAND circuit
552
which receives signals RA
0
and RA
1
and an inverter
554
which inverts by receiving the output of the NAND circuit
552
and outputs a pre-decode signal X
2
.
The pre-decoder
536
includes the pre-decode circuits
556
,
558
, . . . ,
560
which output, respectively, pre-decode signals RX
0
, RX
1
. . . , RX
2047
.
The pre-decode circuit
556
includes a NAND circuit
562
which receives the signals ZRA
2
to ZRA
12
, and an inverter
564
which inverts by receiving the output of the NAND circuit
562
and outputs a pre-decode signal RX
0
.
The pre-decode circuit
558
includes a NAND circuit
566
which receives the signal RA
2
and the signals ZRA
3
to ZRA
12
, and an inverter
568
which inverts by receiving the output of the NAND circuit
566
and outputs a pre-decode signal RX
1
.
The pre-decode circuit
560
includes a NAND circuit
570
which receives the signals RA
2
to RA
12
, and an inverter
572
which inverts by receiving the output of the NAND circuit
570
and outputs a pre-decode signal RX
2047
.
The main decoder
38
includes decode circuits
72
,
74
, . . . ,
76
which activate corresponding word lines in accordance with the respective pre-decode signals RX
0
, RX
1
, . . . , RX
2047
.
The decode circuit
72
includes a NAND circuit
78
which receives the pre-decode signals RX
0
and X
0
, an inverter
80
which inverts by receiving the output of the NAND circuit
78
, a NAND circuit
82
which receives the pre-decode signals RX
0
and X
1
, an inverter
84
which inverts by receiving the output of the NAND circuit
82
, a NAND circuit
86
which receives the pre-decode signals RX
0
and X
2
, an inverter
88
which inverts by receiving the output of a NAND circuit
86
, a NAND circuit
90
which receives the pre-decode signals RX
0
and X
3
, and inverter
92
which inverts by receiving the output of the NAND circuit
90
. The inverters
80
,
84
,
88
and
92
operate as word drivers for driving, respectively, the word lines WL
0
, WL
1
, WL
2
and WL
3
.
Though the decode circuit
74
is different from the decode circuit
72
in the point that the pre-decode signal RX
1
is received in place of RX
0
and the word lines WL
4
to WL
7
are, respectively, activated in place of the word lines WL
0
to WL
3
. Since the circuit configuration of the decode circuit
74
is similar to that of the decode circuit
72
, the description is not repeated.
Though the decode circuit
76
is different from the decode circuit
72
in the point that the pre-decode signal RX
2047
is received in place of RX
0
and the word lines WLn-
3
to WLn are, respectively, activated in place of the word lines WL
0
to WL
3
. Since the circuit configuration of the decode circuit
76
is similar to that of the decode circuit
72
, the description is not repeated.
The row decoder can, finally, select 4×2048, that is to say, 8192 word lines.
FIG. 20
is a view partially showing the manner of memory cell arrangement of the memory cell array
14
as shown in FIG.
18
.
Here, a part of the row decoder and a column decoder as well as sense amplifiers and bit line equalizing circuits are depicted in
FIG. 20
for reference.
Referring to
FIG. 20
, memory cells are arranged in a so-called half pitch configuration. In the half pitch configuration, one cell is surrounded by eight adjacent cells. One of the reasons for

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