Semiconductor integrated circuit device capable of producing...

Details Semiconductor integrated circuit device capable of producing... Semiconductor integrated circuit device capable of producing...

2001-02-21

2002-11-05

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S119000

Reexamination Certificate

active

06476639

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2000-44307, filed on Feb. 22, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor integrated circuit device. More specifically, the invention relates to a semiconductor integrated circuit device capable of producing an output thereof without being influenced by other input/inputs, by improving how to construct a logic gate constituting a clock tree.
The delay time of a signal propagated in an integrated circuit is determined by the input capacitance of a logic gate serving as a load. The input capacitance, i.e., the delay time, in a circuit having a multi-input gate as a load is under the influence of the state of another input signal of the multi-input gate.
FIG. 1
shows a circuit having a two-input NAND gate as a load. In
FIG. 1
, although the input capacitance viewed from an input terminal is (C
1
+C
2
), the input capacitance C
1
of the NAND gate is influenced by the state of another input A.
That is, the apparent capacitance C
1
varies in accordance with the high or low state of the input A. As a result, the delay time of a signal transmitted from the input terminal in to an output terminal out varies. Conventionally, in such a case, a timing design is carried out by supposing the state of the input A in which the delay time of the signal transmitted from the input terminal in to the output terminal out is maximum. In this case, there is a problem in that margin is largish by estimating excessive delay time. In addition, there is some possibility that it is required to suppose the state of the input A, in which the delay time is minimum, to separately carry out a timing check.
Particularly in a clock tree for distributing clock signals to the whole LSI (Large Scale Integrated circuit), it is required to precisely carry out a timing design. In recent years, in order to reduce the electric power consumption of LSIs, there has been used a gated clock technique for partially stopping the supply of clock signals if necessary, such as the art disclosed in Japanese Patent Laid-Open No. 10-308450.
FIG. 2
shows an example of a construction of a gated clock circuit which is disclosed as the prior art in
FIG. 5
of the above described publication. In this circuit, clock signals are inputted as signals
58
a
and
58
b
from a root buffer
51
to NOR circuits
52
a
and
52
b
serving as multi-input gates. When the level of a signal
56
a
or
56
b
outputted from a selector circuit
57
is low, the clock signal is transmitted to a buffer circuit in the next stage, whereas when the level of the signal
56
a
or
56
b
is high, the level of the output is always low, so that the clock signal is not transmitted. Thus, the electric power consumption is reduced by stopping the excessive transition of the clock buffer by the output from the selector circuit
57
.
There is generally no correlation between the operations of logical blocks
60
A and
60
B, so that it is possible to set any combinations of the states of the output signals
56
a
and
56
b
from the selector circuit
57
. Viewed from the root buffer
51
, the input capacitance of the NOR circuit
52
a
and the input capacitance of the NOR circuit
52
b
depend on the states of the signals
56
a
and
56
b
, respectively. For example, the timing in outputting a signal from the NOR circuit
52
a
is different between when the level of the signal
56
b
is high and low. Therefore, the timings in inputting clock signals to flip-flop circuits
55
a
are different.
In general, LSIs are designed so as to operate without causing the shift of all of clock signals inputted to flip-flop circuits
55
a
and
55
b
. The shift of clock signals is called clock skew which must be as small as possible. In the gated clock circuit shown in
FIG. 2
, the input capacitance of the clock signal of the two-input OR-gate of each of the NOR circuit
52
a
and
52
b
is different from each other in accordance with the state of the signal outputted from the selector circuit
57
. Therefore, if the circuit is designed so as to decrease the clock skew by assuming the state of a specific signal of the selector circuit, the clock skew increases in another state.
Thus, it is impossible to carry out a timing design capable of decreasing clock skews in all states. As can be clearly seen from the contents disclosed in
FIGS. 1 and 3
serving as preferred embodiments in the above described Japanese Patent Laid-Open No. 10-308450, this problem on timing design has not been solved.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of designing a logic circuit so that a delay time of a signal propagated in an integrated circuit can be precisely estimated.
In order to accomplish the above object, according to a first basic construction of the present invention, there is provided a semiconductor integrated circuit device capable of producing an output thereof without being influenced by the other inputs, the semiconductor integrated circuit device comprising: a logic circuit designed to process a predetermined logical operation on the basis of an input signal; and an input capacitance equalizing circuit designed to equalize the input capacitance of the logical circuit.
According to a second basic construction of the present invention, there is provided a semiconductor integrated circuit device capable of generating an output thereof without being influenced by the other inputs, the semiconductor integrated circuit device comprising: a logic circuit designed to process a predetermined logical operation on the basis of an input signal; and input capacitance equalizing circuit designed to equalize the input capacitance of the logical circuit, wherein the logic circuit comprises a first logic circuit for carrying out a predetermined logical operation on the basis of a first input signal, and a second logic circuit for carrying out a predetermined logical operation on the basis of at least a second input signal, and an input capacitance equalizing circuit comprises an input capacitance equalizing circuit to which the first input signal is inputted, and wherein the first logic circuit has one or a plurality of the same circuit constructions which are operated by the first input signal, the second logic circuit has one or a plurality of the same circuit constructions to which the one or plurality of second input signals and an output signal outputted from the input capacitance equalizing circuit are inputted, and the input capacitance equalizing circuit is a making input capacitance independence circuit for equalizing the input capacitance of the first input signal without depending on the state of the second input signals.


REFERENCES:
patent: 4803665 (1989-02-01), Kasa
patent: 5391941 (1995-02-01), Landry
patent: 5793551 (1998-08-01), Ngo et al.
patent: 10-308450 (1998-11-01), None

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