Dual data rate transfer on PCI bus

Details Dual data rate transfer on PCI bus Dual data rate transfer on PCI bus

1999-11-24

2002-10-08

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S107000, C710S309000, C710S314000, C710S058000, C710S035000

Reexamination Certificate

active

06463490

ABSTRACT:

FIELD OF THE INVENTION
The invention is related to data transferring on a PCI bus and more particularly to a method and system of transferring data on a PCI bus at a dual data transfer rate.
DESCRIPTION OF THE RELATED ART
An early personal computer(PC) system transferring data between different bus devices on a single bus, typically as the 16-bit ISA bus and 32-bit EISA bus. However, it is difficult to speed up data transferring on these buses because of the limitation of the bit rate and width.
In addition, a bus named Peripheral Component Interconect Bus (PCI Bus) is provided for the computer system having a processor and the above ISA and EISA bus, which is characterized by higher data transferring rate.
At present, the computer system with a PCI bus includes a Host/PCI bus bridge (“host bus bridge” for short here) and a PCI/Expansion bus bridge (“expansion bus bridge” for short here). The former manages data transferring between the PCI bus, the processor and the main memory while the latter manages data transferring between the PCI bus and the expansion bus bridge. In this configuration, it is the host bus bridge through which data is transferred between the main memory and the devices coupled to the PCI bus. Similarly, through the expansion bus bridge and the PCI bus, the devices coupled to the expansion bus transfer data to or from the devices coupled to the PCI bus, and through the host bus bridge, the expansion bus bridge and the PCI bus, transfer data to or from the processor and the main memory.
The PC system
10
shown in
FIG. 1
, for example, mainly includes a processor
12
, a host bus
14
, a Host/PCI bus bridge
16
, a PCI bus
18
, a PCI/Expansion bus bridge
20
and an expansion bus
22
.
Wherein the processor
12
provides various processing signals and performs calculations, operation control and the ordinary works of a processor. Furthermore, the processor
12
is coupled to the host bus
14
and the host bus bridge
16
provides an interface between the host bus
14
and the PCI bus
18
. As for the expansion bus bridge
20
and bus devices
26
having interfaces conformable to the PCI bus specifications such as The PCI Local Bus Specification, Rev 2.1, 1995, they are coupled to the PCI bus
18
. Wide-bandwidth bus devices
26
generally include input/output devices such as a graphic device
26
a
, a LAN device
26
b
, a SCSI device
26
c
and the like. A typical narrow-bandwidth bus device such as a based I/O function device
28
is coupled to the expansion bus
22
. Among various bus devices, those having active access to the memory can be PCI bus masters and the others are merely PCI bus slaves.
The host bus bridge
16
generally include an arbitrator used for arbitrating the competition between the masters for access to the memory so that the one which gains the ownership of the PCI bus
18
is determined. For instance, when various masters desire the access to the memory, each will send a request signal to the arbitrator which determines who will be the winner and granted the ownership of the PCI bus
18
according to the arbitration protocol. Subsequently, the winning master substantially control the PCI bus.
The PCI bus master
27
coupled to the PCI bus
18
, for example, is characterized by including a processor with an internal clock signal by which the master operates and having the ability to initialize and control the operation of the PCI bus.
In addition to establishing communications between the processor
12
and the PCI bus
18
and arbitrating the competition for the ownership of the PCI bus
18
, the functions of the host bus bridge
16
further comprise establishing communications between the memory
24
and the processor
12
, and between the memory
24
and the PCI bus
18
.
The expansion bus bridge
20
is coupled to the PCI bus
18
and the expansion bus
22
to manage the data transferring, the control signals and address signals between the devices coupled to the PCI bus
18
and the expansion bus
22
. The expansion bus bridge
20
also comprises an arbitrator used for arbitrating the competition between the bus devices
28
coupled to the expansion bus
22
, wherein the bus devices
28
and the expansion bus
22
are conformable to the specifications of ISA, EISA or MCA.
As shown in
FIG. 2
, a PCI interface between the host bus bridge
16
and the expansion bus bridge
20
, for example, includes a multiplexed Address/Data signal, AD, a Bus Command/Byte Enables signal, CBE, interface control signals including a Cycle Frame signal, FRAME#, an Initiator Ready signal, IRDY#, a Target Ready signal, TRDY#, a Device Select signal, DEVSEL# and a Stop signal, STOP#, and arbitration signals including a PCI Grant signal, PGNT# and a PCI Request signal, PREQ#.
With reference to
FIG. 4
, a timing diagram of data transferring on the PCI bus
18
is shown.
In addition, as shown in Table 1, complete data transferring on a PCI bus includes an arbitration phase, an address phase and a plurality of data phase. During each of the phases, each signal has a logic level such as logic low, L, logic high, H and floating, X. Besides, according to the timing diagram in
FIG. 4
, the signals are sampled on the rising edges of PCLK, which are indicated by the dotted vertical lines. A # symbol at the end of a signal name indicates that the active state occurs when the signal is at a low voltage.
TABLE 1
Signal
Arbitration
Address
Data
Name
Phase
Phase
Phases
FRAME #
X
L
L, H for the last
data phase of
the transaction
IRDY #
X
H
L
DEVSEL #
X
H
L
CBE
X
Bus Command
Byte Enables
AD
X
Address
Data
STOP #
X
H
Retry or H
TRDY#
X
H
L
PREQ#
Request signal
L
L
PGNT #
Grant signal
L
L
Refer to
FIG. 4
together with
FIG. 1 and 3
, wherein an example illustrating that the expansion bus bridge
20
becoming a master by winning the ownership of the PCI bus writes or reads the memory through a target (i.e. a selected device) such as the host bus bridge
16
. The procedure of data transferring includes:
According to the step S
10
, PREQ# of the master is asserted.
According to the step S
12
, proceed to the next step when PGNT# of the arbitrator is asserted.
According to the step S
14
, FRAME# of the master is asserted and the master begins to drive the address signal AD.
According to the step S
16
, proceed to the next step when DEVSEL# of the target is asserted.
According to the step S
18
, when TRDY# of the target is asserted, the target begins to drive the data signal AD and the first data transfer occurs on the next rising edge of PCLK.
According to the step S
20
, proceed to the next step when the current data phase is the last one of the current transaction. According to step S
22
, FRAME# and PREQ# of the master are deasserted. According to step S
24
, PGNT# of the target is deasserted. Finally, According to step S
26
, the current transaction ends and the data transferring is completed. Wherein a read or write transaction starts with an address phase when FRAME# is asserted. During the address phase, AD contain a valid address and CBE contain a valid bus command. In addition, during a write transaction, IRDY# indicates that valid data is present on AD. During a read transaction, it indicates the master is prepared to accept data. Correspondingly, during a read transaction, TRDY# indicates that valid data is present on AD. During a write transaction, it indicates the target is prepared to accept data.
STOP# indicates the current target is requesting the master to stop the current transaction. (It is not asserted in the present example.)
However, one of the problems of the conventional system described above is the lack of the bandwith caused by the buck data transferring of the devices with high transfer rates coupled to the expansion bus bridge, such as IDE-DMA66. To solve the above problem, a method of transferring data in PCI idle clock cycles is provided in the U.S. Pat. No. 5790811.
SUMMARY OF THE INVENTION
As an alternative way to solve the problem

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