Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-07-25
2002-06-11
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S723000, C257S737000
Reexamination Certificate
active
06404063
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention: This invention relates generally to die-to-insert interconnections and, more specifically, to a method of forming a permanent die-to-insert electrical connection for a semiconductor die assembly by diffusing gold bumps on the insert into the bond pads of the die using relatively low elevated temperatures and low levels of constant force during the extended time of a burn-in process.
State of the Art: Currently, there are three primary chip-level interconnection technologies in practice. They include wirebonding (WB), Tape Automated Bonding (TAB), and Controlled Collapse Chip Connection (C
4
). The method used to bond the interconnections is dependent upon the number and spacing of input/output (I/O) connections on the chip and the insert (i.e., substrate) as well as permissible cost.
WB is the most common chip-bonding technology because the required number of chip connections in many products can be accomplished in addition to providing the lowest cost per connection. WB is generally employed to electrically connect chips to the inner ends of the leads of a lead frame, the assembly subsequently being packaged as by transfer molding of a plastic package. For chips requiring more than 257 but less than 600 connections, TAB may be used. TAB employs lead frames of a finer pitch mounted on an insulative carrier tape which is integrated into the chip package. The C
4
process, however, is capable of creating up to 16,000 connections per chip (or partial wafer), potentially meeting the demand for any number of connections that the die or partial wafer design dictates.
When C
4
bonding is employed, the entire surface of the chip is normally covered with bond pads for the highest possible I/O count. Solder bumps are deposited on wettable metal terminals (bond pads) on the chip, and a matching footprint of solder-wettable terminals is located on the substrate. Both the bond pads and the terminals must be treated with solder flux. Moreover, the solder bumps must be constrained from completely collapsing (or flowing out onto the substrate bonding site) by using thick-film glass dams, or stops. The tendency for the solder to flow on the chip is contained by a special bonding pad metallurgy that consists of a circular pad of evaporated chromium, copper, and gold. The bond pad metallurgy is then coated by evaporation with, for example,
5
Sn-
95
Pb or
2
Sn-
98
Pb, to a thickness of 100 to 125 &mgr;m. Finally, the upside-down chip or die (flip-chip) is aligned to the substrate, and all chip-to-substrate conductive paths are made simultaneously by reflowing the solder.
The numerous process steps and extensive prebond preparation associated with C
4
makes it an expensive bonding method. Moreover, because of the expense added by the C
4
process, bumping the chip has been avoided. In the Very Large Scale Integration (VLSI) era, however, the expense has been necessary to obtain the required number of connections.
As disclosed in U.S. Pat. No. 5,435,734 to Chow, pressure contact interconnect methods are also known in the art. Pressure contacts are not actually bonded but rather form a continuous contact using a material deformation concept such as a metal spring or an elastic retainer. For example, two gold bumps (on chip and substrate) may be joined by a conductive rubber contact embedded in a polyamide carrier. However, this is a mechanically created connection and is, therefore, not as desirable as metallurgical bonding techniques for economic- as well as reliability-associated reasons.
Furthermore, all of the previously mentioned methods of forming chip-to-substrate interconnections are typically effected after a burn-in operation is performed on the chip to determine if the chip is defective. For burn-in, a chip is typically placed in a multi-chip carrier in resiliently biased or other temporary connection to a burn-in die or substrate (also called an insert) having circuit traces and contacts for electrical testing of the chip. During the burn-in process, the chips are generally subjected to electrical impulses and elevated temperatures (on the order of 125-150° C.) for extended periods of time, usually 24-48 hours, depending upon the chip and the characterization protocol. Low-temperature cycling to as low as −50° C. may also be employed on occasion, particularly for chips being qualified to military specifications. However, this is not common for chips destined for use in commercial applications.
If not proven defective, the chip is removed from its test fixture after burn-in and is then permanently attached to a substrate by means known in the art, such as those previously mentioned. Alternatively, the chip may be wirebonded to a lead frame or TAB-bonded to a taped lead frame, as known in the art, depending upon the ultimate application for the chip and preferred packaging for that application. In any case, burn-in connections and permanent operational connections are effected in the prior art in two distinct and different operations. While it would be possible to form permanent die-to-insert connections before burn-in, this would increase processing time and cost. It is known to package single die before burn-in, such as with wire- or TAB-bonded lead frame-mounted, plastic-packaged dice (e.g., DIP, ZIP), but such arrangements are not suitable for multi-chip modules (MCM's) such as single in-line memory modules (SIMM's) where failure of a single die will result in scrapping of the module.
Thus, it would be advantageous to provide an economical method of chip-to-substrate interconnection that is capable of keeping up with the ever-increasing requirements for more I/O connections per chip, does not require all of the preparation and process steps associated with C
4
chip interconnections such as application of flux and the use of thick-film glass substrate dams, and removes at least one major step from the manufacturing process through use of a one-step chip-to-substrate electrical connection technique suitable for both burn-in and ultimate first-level packaging of a chip.
Additional non-C
4
ball- or bump-type chip-to-substrate electrical interconnect systems exist in the art, as disclosed in U.S. Pat. Nos. 5,451,274; 5,426,266; 5,369,545; 5,346,857; and 5,341,979. Such systems achieve electrical connections through use of relatively complex and sophisticated apparatus and process methodology, and thus are not suitable for use during chip burn-in in a carrier or other fixture.
Temporary chip-to-burn-in die or insert connections are also known in the art and exemplified by the disclosures of U.S. Pat. Nos. 5,440,241; 5,397,997; and 5,249,450. None of the foregoing patents, however, discloses a methodology for forming suitably permanent die-to-substrate electrical connections during burn-in.
It is known in the electronics art to employ diffusion bonding to effect electrical connections between two or more substrates or circuit boards; U.S. Pat. No. 5,276,955 discloses such a process. However, diffusion bonding as known in the art is generally effected at relatively high temperatures just below the eutectic or peritectic temperatures of the bonding alloy, and for relatively short periods of time, such as one or two hours. Thus, state-of-the-art diffusion bonding as known to the inventors has no legitimate application to making chip-to-insert connections.
BRIEF SUMMARY OF THE INVENTION
According to the invention, a method for forming a permanent chip-to-insert interconnection is herein disclosed. Gold bumps are attached to ends of conductive circuit traces on one side or the other of a nonelectrically conductive substrate, or even the exposed ends of internal conductors, by which electrical testing of a chip during burn-in is effected. As used herein, it should be understood that the term “gold” includes not only elemental gold, but gold with other trace metals and in various alloyed combinations with other metals as known in the semiconductor art. Typically, the die has bond pads on one surface (commonly termed the “fron
Farnworth Warren M.
Wood Alan G.
Micro)n Technology, Inc.
Potter Roy
TraskBritt
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