Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-27
2002-04-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S761000
Reexamination Certificate
active
06376888
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-124405, filed Apr. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to an improvement of a gate electrode for an N-type MIS transistor and a P-type MIS transistor.
2. Description of the Related Art
For improving the performance of the MIS transistor, it is absolutely necessary to make the device finer. However, a silicon oxide film used nowadays as a gate insulating film is low in its dielectric constant, giving rise to the problem that it is impossible to increase the capacitance of the gate insulating film. Also, a polycrystalline silicon (polysilicon) used as a gate electrode has a high resistivity, resulting in failure to lower the resistance. To overcome these problems, it is proposed to use a film having a high dielectric constant for forming the gate insulating film to use a metallic material for forming the gate electrode.
However, these materials are poor in heat resistance, compared with the materials used nowadays. Under the circumstances, proposed is a damascene gate technology that permits forming a gate insulating film and a gate electrode after a high temperature process.
In the damascene gate technology, a dummy gate is formed in advance in a region where a gate is to be formed later. The dummy gate is removed after formation of the source-drain diffusion layers, and an electrode material is buried in the region from which the dummy gate has been removed so as to form a gate electrode.
If the same material is used for forming the gate electrodes of the N-type and P-type MIS transistors in the case of forming the gate electrode by employing the damascene gate technology, it is impossible to make the gate electrodes of these transistors differ from each in the work function. As a result, it is impossible to make appropriate the threshold voltage of each of the N-type and P-type MIS transistors. Therefore, a manufacturing process using different gate electrode materials is required for manufacturing an N-type MIS transistor and a P-type MIS transistor.
FIGS. 15A
to
15
I collectively exemplify such a manufacturing process.
In the first step, an element isolating region
502
of an STI structure is formed on a silicon substrate
501
, as shown in FIG.
15
A. Then, a silicon oxide film
503
is formed in a thickness of about 6 nm as a dummy insulating film that is to be removed later. Further, a laminate structure consisting of a polysilicon film
504
having a thickness of about 150 nm and a silicon nitride film
505
having a thickness of about 50 nm is formed as a dummy gate that is to be removed later. These dummy insulating film and dummy gate are formed by the ordinary technology such as a film-forming technology including an oxidation, CVD and the like, lithography technology, and RIE technology. After formation of the dummy gate, impurity ions are implanted by using the dummy gate (the polysilicon film
504
and the silicon nitride film
505
) as a mask to form a diffusion layer for extension for forming source-drain diffusion layers
506
. Then, a gate side wall insulating film consisting of a silicon nitride film
507
having a width of about 40 nm is formed by the CVD technology and the RIE technology, as shown in FIG.
15
A.
In the next step, impurity ions are implanted by using the dummy gate (the polysilicon film
504
and the silicon nitride film
505
) and the gate side wall insulating film (silicon nitride film
507
) as a mask to form impurity diffusion layers having a high impurity concentration, said impurity diffusion layers constituting source-drain diffusion layers
508
. Then, a silicide film
509
having a thickness of about 40 nm (cobalt silicide film or a titanium silicide film) is formed in only the source-drain regions by the salicide process technology, as shown in FIG.
15
B.
In the next step, an interlayer insulating film
510
is formed, for example, a silicon oxide film by a CVD method. Then, the interlayer insulating film
510
is flattened by a CMP technology so as to expose the surfaces of the silicon nitride films
505
and
507
, as shown in FIG.
15
C.
Further, the silicon nitride film
505
in an upper portion of the dummy gate is selectively removed by using a phosphoric acid relative to the interlayer insulating film
510
. In this step, the silicon nitride film
507
is also etched to the height of the polysilicon film
504
. Then, the polysilicon film
504
is selectively removed by the etching technology using radicals of halogen atoms such as fluorine atoms, as shown in FIG.
15
D.
In the next step, a groove is formed by removing the dummy silicon oxide film
503
by a wet etching using, for example, hydrofluoric acid, followed by forming a Ta
2
O
5
film
512
, which is a high dielectric constant film, as a gate insulating film by, for example, a CVD method. Further, an aluminum film
513
, is deposited to form a gate electrode, as shown in FIG.
15
E. After formation of the aluminum film
513
, the Ta
2
O
5
film
512
and the aluminum film
513
are flattened until the interlayer insulating film
510
is exposed to the surface, as shown in FIG.
15
F.
The steps shown in
FIGS. 15A
to
15
F are applied to both the N-type MIS transistor forming region and the P-type MIS transistor forming region, though only one region is shown in the drawings. In the subsequent steps, however, both the N-type MIS transistor (N-type MISFET) forming region and the P-type MIS transistor (P-type MISFET) forming regions are shown in the drawings.
After the step shown in
FIG. 15F
, the entire surface except the P-type MIS transistor forming region is covered with a resist layer
514
by using a lithography technology, as shown in FIG.
15
G. Then, the aluminum film
513
in only the P-type region is removed by the wet etching using a phosphoric acid. In this step, the silicon nitride film
507
, which is exposed to the surface, is scarcely etched with phosphoric acid under room temperature, as shown in FIG.
15
H.
In the next step, the resist layer
514
is removed and a metal having a work function of about 5 eV, e.g., a cobalt film
515
, is deposited on the entire surface, as shown in FIG.
15
I. Finally, the cobalt film
515
is flattened by a CMP technology until the interlayer insulating film
510
is exposed to the surface, as shown in FIG.
15
J.
In the semiconductor device manufactured by the process described above, the aluminum film
513
forms the gate electrode of the N-type MIS transistor, and the cobalt film
515
forms the gate electrode of the P-type MIS transistor so as to provide a C-MIS transistor. It should be noted that the aluminum film
513
has a work function of about 4.2 eV and the cobalt film
515
has a work function of about 5 eV. It follows that it is possible to make appropriate the work function of the gate electrode in each of the N-type MIS transistor and the P-type MIS transistor. As a result, it is possible to make appropriate the threshold voltage of each of the N-type and P-type MIS transistors.
However, the conventional technology described above gives rise to a serious problem in terms of miniaturization of the device. The particular problem will now be described.
FIGS. 16A
,
16
B and
16
C are plan views schematically showing the constructions in the main portions of
FIGS. 15G
,
15
H and
15
J, respectively. The distance between the source-drain regions of the N-type MIS transistor and the source-drain regions of the P-type MIS transistor, i.e., the distance between the devices, is set at D.
If the aluminum film
513
in the P-type region is subjected to a wet etching using the resist layer
514
as a mask in the step shown in
FIG. 15H
, the wet etching proceeds isotropically. Thus, the etching proceeds deep into the region masked by the resist laye
Iinuma Toshihiko
Matsuo Kouji
Murakoshi Atsushi
Suguro Kyoichi
Tsunashima Yoshitaka
Finnegan, Henderson, Farabow, Garrett & Dunner. L.L.P.
Nelms David
Nhu David
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