Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-13
2002-07-23
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S311000, C257S314000
Reexamination Certificate
active
06423997
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority application No. 11-067390 filed on Mar. 12, 1999, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a semiconductor integrated circuit in which a capacitor and a floating-capacitor are integrated on a common substrate.
Semiconductor memory devices are used extensively in various information processing apparatuses and controllers including computers together with logic operation devices such as a microprocessor. Particularly, there is a type of semiconductor memory device called non-volatile semiconductor memory device in which information is stored in a floating gate in the form of electric charges. Typical examples of the non-volatile semiconductor memory device includes EPROMs and flash memory devices. In such a non-volatile semiconductor memory devices, the information is maintained even when the electric power is turned off.
In these days, there is a demand for a so-called mixed integrated circuit in which a flash memory device is integrated with an analog device on a common semiconductor substrate. As it is usual that an analog device includes a capacitor, there is a demand for a technology to form an ordinary capacitor of the analog device and the floating capacitor of the flash memory simultaneously on a common semiconductor substrate.
FIGS. 1A-1F
show the fabrication process of a mixed integrated circuit
10
according to a related art in which a flash memory device and an analog capacitor are integrated.
Referring to
FIG. 1A
, a p-type Si substrate
11
is formed with a field oxide film
12
such that the field oxide film
12
defines a flash memory region
11
A and an analog circuit region
11
B on the Si substrate
11
. In correspondence to analog circuit region
11
B, there is formed an n
+
-type diffusion region
11
b
in the Si substrate
11
by conducting an ion implantation process of As
+
with a dose of 1×10
15
-10
16
cm
−2
while using an acceleration voltage of 50-500 keV. The n
+
-type diffusion region
11
b
thus formed serves for a lower electrode of the analog capacitor to be formed.
In the step of
FIG. 1A
, a tunneling oxide film
11
a
is formed further on the Si substrate
11
in correspondence to the flash-memory region
11
A as a result of thermal oxidation process of the Si substrate
11
.
In the step of
FIG. 1A
, it should further be noted that a polysilicon film is deposited on the Si substrate
11
by a CVD process so as to cover the tunneling oxide film
11
a
with a thickness of typically 100-150 nm, and a floating gate electrode
13
of the flash-memory device is formed on the flash-memory region
11
A as a result of the patterning of the polysilicon film thus formed. Further, an insulation film
14
having an ONO structure, in which an SiN film is vertically sandwiched by a pair of SiO
2
films, is formed on the semiconductor structure thus formed with a thickness of 20-30 nm.
Next, in the step of
FIG. 1B
, a resist pattern
15
is formed on the structure of FIG.
1
A and the insulation film
14
is subjected to a dry etching process while using the resist pattern
15
as a mask. As a result of the dry etching process, the insulation film
14
is left only on the flash-memory region
11
A as the interlayer insulation film of the flash memory device.
After the foregoing process, the resist pattern
15
is removed and a thermal oxidation process is conducted in the step of FIG.
1
C. As a result of the thermal oxidation process, there is formed a gate oxide film
16
on the Si substrate
11
. Further, such a thermal oxidation process induces an oxidation in the SiN film constituting the ONO structure, and there is formed a thin oxide film
16
A on the insulation layer
14
.
As represented in
FIG. 1C
, the oxidation process is accelerated in the analog circuit region
11
B in correspondence to the n
+
-type diffusion region
11
b
doped with As, and the thickness of the gate oxide film
16
is increased for a part represented by a reference numeral
16
B. The region
16
B of the thermal oxide film
16
is used for the capacitor insulation film of the capacitor to be formed.
Next, in the step of
FIG. 1D
, a composite conductive film of a polysilicon layer and a WSi layer is deposited on the structure of
FIG. 1C
, and an upper electrode
17
B of the analog capacitor is formed on the analog circuit region
11
B as a result of the patterning of the conductive film thus formed while using resist patterns
18
A and
18
B as a mask. The upper electrode
17
B thus formed covers the region
16
B of the thermal oxide film
16
. It should be noted that a control gate electrode
17
A is formed simultaneously in the flash-memory region as a result of the foregoing patterning of the conductive film.
Next, in the step of
FIG. 1E
, a resist pattern
19
B is formed on the structure of
FIG. 1D
so as to cover the analog circuit region
11
B, and a resist pattern
19
A is formed in the flash-memory region
11
A such that the resist pattern
19
A covers a part of the control gate electrode
17
A. By conducting a dry etching process through the control electrode
17
A, the thermal oxide film
16
A, the ONO film
14
and the floating gate
13
consecutively while using the resist patterns
19
A and
19
B as a mask, a gate electrode structure G is formed as represented in FIG.
1
E.
Finally, the resist patterns
19
A and
19
B are removed and an ion implantation process of As
+
or P
+
is conducted under an acceleration voltage of typically 50-80 keV and a dose of 1×10
15
-10
16
cm
−2
while using the control gate electrode
17
A and the upper electrode
17
B as a mask. As a result of the ion implantation process, there are formed n-type diffusion regions
11
c
and
11
d
in the Si substrate at both lateral sides of the gate electrode structure G. Further, there is formed another diffusion region
11
e
in the analog circuit region
11
B as a result of the foregoing ion implantation process, such that the diffusion region
11
e
extends from the diffusion region
11
b
to the field oxide film
12
.
In the structure of
FIG. 1F
, it can be seen that a flash-memory cell having the gate electrode structure G is formed in the flash-memory region
11
A defined on the Si substrate
11
and that an analog capacitor C having the diffusion region
11
b
as the lower electrode, the oxide film
16
B as the capacitor insulation film and the polysilicon electrode
17
B as the upper electrode, is formed on the same Si substrate
11
in correspondence to the analog circuit region
11
B. Thereby, the flash-memory cell and the analog capacitor C are formed substantially simultaneously.
Thus, the foregoing process of the related art enables the formation of a flash memory device and an analog capacitor substantially on the same Si substrate. On the other hand, the capacitor thus formed has a drawback in that the analog circuit cooperating with the analog capacitor is vulnerable to electrical noise propagating through the substrate or change of the substrate bias voltage. As can be seen in
FIG. 1F
, the lower electrode
11
b
of the capacitor C is formed in the Si substrate in the form of a diffusion region.
Further, the mixed integrated circuit of the prior art formed according to the process of
FIGS. 1A-1F
suffers from the problem of increased thickness of the capacitor insulation film
16
B, which is caused in the step of
FIG. 1C
for oxidizing the Si substrate
11
for forming the gate oxide film
16
. As noted previously, there occurs an acceleration of oxidation in the diffusion region
11
b
doped to the n
+
-type.
It should be noted that the foregoing problem of accelerated oxidation appears conspicuously when conducting the oxidation process at a low temperature by using a wet oxidation technique so as to form the gate oxide film
16
with a uniform thickness. There can be a
Armstrong Westerman & Hattori, LLP.
Chaudhuri Olik
Fujitsu Limited
Pham Hoai
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