Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
1999-08-31
2002-04-02
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
75, 75
Reexamination Certificate
active
06365977
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a new structure and a method for reducing the cost of producing known good die (KGD). More particularly, the invention encompasses a structure and a method that uses a substrate having solder wettable pads, a chip with attached solder balls, and a thin non-conductive interposer that is assembled between the chip and the substrate. The interposer reduces the cross section of the solder connections from the chip to the substrate where the solder passes through (the holes in) the interposer. This reduced cross-sectional area of the solder connection creates a weak point which allows the chip to be easily sheared off of the substrate after a burn-in and test process. The preferred chips for this invention are flip chips.
BACKGROUND OF THE INVENTION
Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produce a corresponding emphasis on overall chip packaging strategies in order to remain competitive. Chip and chip substrate manufacturers are therefore constantly being challenged to improve the quality of their products by identifying and eliminating problems, reducing package size and weight, decreasing package costs, providing improved thermal efficiencies and producing better and more advanced chips. Whereas significant improvements are being made to eliminate systematic problems by reducing process variability, process improvements alone are not sufficient to eliminate all the problems which effect both performance and reliability.
One way to improve device density and improve performance is to use multi-chip modules (MCMs). Certain chip defects are not detectable until the chip is mounted onto a substrate. Other chips have latent defects which appear early in use. These latent defects often have their lives accelerated, and are caused to fail during manufacturing processes, via various burn-in operations. In either case, once a defective chip has been detected, expensive rework processes are required to replace the defective component and avoid the loss of the other devices on the module. If the module has many chips or if the chips have low yields, the required rework steps could be numerous, which could be cost prohibitive, and possibly degrade the reliability of the substrate.
One way to reduce the cost of assembling MCMs is to use known good die (KGD). Therefore, the availability of KGD is an important factor in bringing MCMs into the marketplace.
Traditional methods of producing KGD involves joining chips temporarily to special substrates. However, these processes are rather expensive as they involve the use of expensive plating operations. The temporarily attached chip on the substrate is then subjected to burn-in and test. Having survived these processes the chips are then sheared from the burn-in and test substrates and remounted (permanently) onto a product substrate. Therefore, a reduction in the cost of temporary chip attach (TCA) substrates reduces the cost of KGD, which further allows the cost competitiveness of MCMs in the marketplace.
One way to reduce the cost of TCA substrates, KGD, and MCMs is to develop a structure and a method for producing KGD that uses conventional single chip module (SCM) substrates, but does not require the use of expensive plating processes. One way to eliminate the need for these plating processes is to invent an interposer or a separator that can be assembled between a standard flip chip and a standard substrate, where the interposer or separator significantly reduces the cross sectional area of the flip chip solder connections, so that the connections may be easily sheared after a burn-in and test process.
U.S. Pat. No. 5,111,279 (Pasch), U.S. Pat. No. 5,168,346 (Pasch), U.S. Pat. No. 5,347,162 (Pasch) and U.S. Pat. No. 5,569,963 (Rostoker), all related to each other and assigned to LSI Logic Corporation, disclose a preformed planar structure that is interposed between the chip(s) and the substrate in a flip-chip structure. This type of a structure establishes a minimum gap between the chip(s) and the substrate. These patents also disclose that the interposer could be dissolvable. Also disclosed is that the through holes may be angled so that the interposer acts as a pitch spreader or adapter.
U.S. Pat. No. 5,237,269 (Aimi) assigned to International Business Machines Corporation, the disclosure of which is incorporated herein by reference, discloses connections between circuit chips and a temporary carrier for use in burn-in tests, in which frangible connections are made between contact points of a reusable carrier and a chip to be tested. After the burn-in test, shear force is imparted such that the frangible connections are broken without causing damage to the chip or the carrier. Also disclosed is the fact that the solder balls could be reflowed to reshape them for subsequent use.
U.S. Pat. No. 5,494,856 (Beaumont) assigned to International Business Machines Corporation, the disclosure of which is incorporated herein by reference, discloses an apparatus and method for creating detachable solder connections between two surfaces which connections are relatively weak and thus can be readily fractured for separating the surfaces. Basically, the surface of the pad on the carrier has a matrix of solder wettable and solder non-wettable areas, and once the solder balls on the chip are attached to the treated pads the electrical contacts are made, and the chip can be readily removed after the test.
Therefore, there is a need for a low cost interposer that can be used with conventional substrates, to establish weak solder connections to flip chips that can easily be sheared after burn-in and/or test.
PURPOSES AND SUMMARY OF THE INVENTION
The invention is a novel method and a structure for temporarily joining one electrical component to another electrical component with an interposer or separator in-between, wherein the interposer/separator provides a substantially reduced electrical contact area where the electrical connection passes through (the holes in) the interposer/separator. This reduced cross-sectional area of the electrical connection creates a weak point which allows one of the electrical component to be easily sheared off of the other electrical component after a burn-in and test process.
Therefore, one purpose of this invention is to provide a structure and a method that will provide a reduced electrical and physical contact area between two electrical components.
Another purpose of this invention is to provide a low cost assembly for the generation of KGD.
Still another purpose of this invention is to generate solder connections that are strong enough to survive burn-in and test operations.
Yet another purpose of this invention is to generate solder connections that are weak enough that they are easily sheared after the completion of the burn-in and test operations.
Still another purpose of this invention is to be able to use and re-use a product-like substrate in the production of KGD.
Yet another purpose of this invention is to provide a low cost interposer to eliminate the need for expensive substrate plating processes.
Therefore, in one aspect this invention comprises an insulative separator having at least one hole to provide at least one nipple-like electrical contact between two electrical components.
In another aspect this invention comprises a structure for temporarily attaching at least one chip to a substrate comprising:
(a) a chip having at least one solder ball,
(b) a substrate having at least one solder wettable pad, said pad corresponds to said solder ball on said chip, and
(c) at least one insulating interposer having at least one through hole, wherein said hole reduces the physical surface connection between said solder ball and said pad.
In yet another aspect this invention comprises a method of joining two electrical components with a separator in-between comprising.
(a) placing a separator having at least one hole on a first electrical component, such that at le
Dauerer Norman J.
Daves Glenn G.
Edwards David L.
Clark Sheila V.
Pepper Margaret A.
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