Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-04-20
2002-09-24
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000, C438S720000
Reexamination Certificate
active
06455435
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating a wiring plane of switching elements on a semiconductor chip with an antifuse.
Antifuses are used as programmable components in integrated circuits in order to provide the user with the opportunity to program functions of the circuit himself. Furthermore, in semiconductor memories antifuses are used to provide circuit redundancy, i.e. in order, e.g. in the case of a data memory cell, to connect up a redundant memory cell by activation of the antifuse.
In this case, antifuses generally contain two electrically conductive contacts between which an insulating layer is introduced (e.g. U.S. Pat. No. 5,763,898). In this case, the material of the insulating layer is chosen such that it is destroyed by the action of energy, e.g. by radiating in a laser beam or applying a high voltage to the electrically conductive contacts, as a result of which a conductive connection is produced through the originally insulating layer and the two external conductive contacts are thus short-circuited. The antifuse can thus be switched from the off state to the on state in a manner programmed by the action of energy.
In this case, antifuses can be fabricated from a wide variety of electrically conductive materials as contacts and also from a wide variety of insulating intermediate layers disposed between the contacts. The antifuses are preferably fabricated, however, in the context of forming the metal planes in the semiconductor chip for wiring the switching elements of the integrated circuit or for connecting these components to the external connections of the semiconductor chip. In this case, the following process sequence is conventionally carried out in order to form antifuses in the context of metallization of the semiconductor chip. In order to fabricate the wiring plane, an oxide layer is coated on the semiconductor chip, contact holes to the components in the semiconductor chip being defined on the oxide layer by photolithography. At these contact points, the oxide is then removed preferably by chemical-physical dry etching. The uncovered contact holes are filled with a conductive material, e.g. polysilicon or a metal. The filling material is subsequently removed again by being etched back outside the contact holes, depressions being formed in the contact holes.
A dielectric layer, preferably silicon nitride, silicon dioxide or silicon oxynitride, is then deposited, on which the interconnects are defined in a further lithography process. During the lithography process, a photoresist containing two layers is applied to the dielectric layer by spinning. The two-layer photoresist contains a lower organic antireflection layer which may be a photoresist or resin thereof which is made highly light-absorbing by an absorber addition or by baking. The actually photochemically active photoresist layer is then applied to the organic antireflection layer. The lower organic antireflection layer serves to ensure that practically no light is reflected back from the semiconductor surface into the upper light-sensitive photoresist layer, thereby avoiding interference effects that prevent profile-exact transfer of the mask structure to the photoresist during exposure.
After exposure, the upper photoresist layer is developed, the irradiated regions of the photoresist are removed. The remaining photoresist regions serve as an etching mask for anisotropic etching of the organic antireflection layer, in order to transfer the structure produced in the upper photoresist layer to the dielectric layer situated under the organic antireflection layer. Afterward, in a next etching step during which the organic antireflection layer serves as a mask, the dielectric layer and parts of the underlying material are then removed, interconnect trenches thereby being produced. All of the remaining photoresist is then removed and a metallic material, primarily tungsten, is deposited on the surface in a large-area manner. The etched trenches which serve as interconnects and also the depressions—covered with a dielectric layer—in the remaining contact holes into which no interconnects were etched being filled. Afterward, the metallic material is then removed again outside the trenches and the depressions in the contact holes. The trenches filled with the conductive material serve as interconnects for wiring the components of the semiconductor chip, while the filled contact holes, with the dielectric layer situated between the conductive materials, are used as the antifuses.
In the conventional process sequence for fabricating antifuses in the context of metallization, it is necessary, as explained, to carry out two etching operations in order to form the interconnects, first the organic antireflection layer and then the underlying dielectric layer, which is required as the antifuse dielectric, being removed. During the operation of etching the organic antireflection layer, in particular the material deposited in the contact holes on the dielectric layer must also be reliably removed in the process, which is possible only by very precise process control. During the successive operations of etching the organic antireflection layer and the dielectric layer, care must furthermore be taken to ensure that compatibility between the different etching processes is achieved, otherwise the two etching operations have to be carried out in two different reaction chambers, thereby significantly increasing the fabrication costs.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a wiring plane on a semiconductor chip with an antifuse which overcomes the above-mentioned disadvantages of the prior art methods of this general type, which is distinguished by simple process control and low fabrication costs.
With the foregoing and other objects in view there is provided, in accordance with the invention, a fabrication method. The method includes the steps of providing a chip having a chip surface, applying a dielectric layer having a buried antireflection layer on the chip surface, photolithographically defining contact holes to be formed in the dielectric layer, etching the contact holes into the dielectric layer, applying a large-area application of a conductive material, removing the conductive material outside of the contact holes, forming depressions in the conductive material filling in the contact holes, applying a large-area application of an insulating layer, photolithographically defining interconnects to be formed in a region of some of the contact holes on the insulating layer, etching interconnect trenches into the insulating layer and the dielectric layer, applying a large-area application of a further conductive material, and removing the further conductive material from areas outside the interconnect trenches and the depressions. A combination of the further conductive material in the depressions, the insulating layer under the further conductive material and the conductive material under the insulating layer forming antifuses.
The process control for simultaneously forming the interconnects and the antifuses, which are both formed in the region of the depressions in the contact holes, makes it possible to carry out the etching of the interconnects in a single etching step. During which the insulating layer is removed in the region provided for the interconnects, thereby resulting in a simplified and cost-effective process progression. In this case, the antireflection layer buried in the dielectric layer reliably ensures that, during the photolithography for defining both the contact holes and the interconnects, interference effects are avoided during exposure.
In accordance with a preferred embodiment, the buried antireflection layer is composed of a light-absorbing inorganic material, preferably an oxynitride, and has a layer thickness of between 15 and 60 &mgr;m. The material can be incorporated particularly well as an intermediate layer into the dielectric, in particular an oxid
Lehr Matthias
Leiberg Wolfgang
Chen Kin-Chan
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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