Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1997-04-23
2002-09-17
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S100000
Reexamination Certificate
active
06453399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a computer, and in particular to a semiconductor memory device which produces a signal indicative of the fact that output is fixed in the operation of outputting stored data as well as a computer provided with this semiconductor memory device.
The semiconductor memory device according to the invention is applicable to any kinds of computer such as a super computer, a large scale computer, a work station and a personal computer.
2. Description of the Related Art
FIG. 1
shows a conventional semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In
FIG. 1
, an RAM (Random Access Memory)
1
receives address signals A
0
, A
1
, . . . as well as a control signal CTR which includes a row address strobe signal {overscore (RAS)}, a column address strobe signal {overscore (CAS)} and a write enable signal {overscore (WE)}, if it is a DRAM, or control signal CTR includes a chip select signal {overscore (CS)} and a write enable signal {overscore (WE)}, if it is an SRAM. In accordance with a state of control signal CTR, RAM
1
writes externally applied input data D
in
into memory cells selected by address signals A
0
, A
1
, . . . , or reads potentials corresponding data stored in memory cells selected by address signals A
0
, A
1
, . . . for externally applying the same as output data D
out
.
A read operation of the conventional semiconductor memory device thus constructed will be described below with reference to timing charts of
FIGS. 2 and 3
.
FIG. 2
is the timing chart showing the read operation in the case where RAM
1
is the SRAM. In the read operation, chip select signal {overscore (CS)} is set to the L-level as shown at (a) in
FIG. 2
to activate the SRAM, and write enable signal {overscore (WE)} is set to the H-level as shown at (b) in FIG.
2
. Externally applied address signals A
0
, A
1
, . . . change at time t
0
as shown at (c) in FIG.
2
.
In accordance with data stored in the memory cells selected by address signals A
0
, A
1
, . . . , output data D
out
changes its state, as shown at (d) in
FIG. 2
, from a high impedance (Hi-Z) state to the H-level or L-level at time t
1
when an address access time t
AAC
(e.g., 10 ns) elapses from the time to of change of address signals A
0
, A
1
, . . . When chip select signal {overscore (CS)} is set to the H-level at time t
2
as shown at (a) in
FIG. 2
, the SRAM is deactivated, and output data D
out
attains the high impedance (Hi-Z) state again as shown at (d) in FIG.
2
.
FIG. 3
is the timing chart showing the read operation in the case where RAM
1
is the DRAM. Before time t
0
at which row address strobe signal {overscore (RAS)} falls to the L-level as shown at (a) in
FIG. 3
, address signals A
0
, A
1
, . . . are set to the X-address of the memory cell to be selected as shown at (d) in FIG.
3
. When row address strobe signal {overscore (RAS)} falls to the L-level at time t
0
as shown at (a) in
FIG. 3
, the DRAM responding it takes in and latches the same using address signals A
0
, A
1
, . . . as the X-address. Then, write enable signal {overscore (WE)} is set to the H-level at time t
1
as shown at (c) in
FIG. 3
, and the DRAM responds to the same and is controlled to perform the reading.
Column address strobe signal {overscore (CAS)} is raised to the L-level at time t
3
as shown at (b) in FIG.
3
. At time t
2
preceding time t
2
, address signals A
0
, A
1
, . . . are set to the Y-address of the memory cell to be selected as shown at (d) in FIG.
3
. Column address strobe signal {overscore (CAS)} falls to the L-level at time t
3
as shown at (b) in FIG.
3
. In accordance with data stored in the memory cell selected by the X-address and Y-address, output data D
out
changes its state from the high impedance (Hi-Z) state to the H-level or L-level at time t
4
after elapsing of an {overscore (RAS)} access time t
RAS
(e.g., 50 ns) from time to and hence after elapsing of a {overscore (CAS)} access time t
CAS
from time t
3
. When column address strobe signal {overscore (CAS)} is raised to the H-level at time t
5
as shown at (b) in
FIG. 3
, output data D
out
attains the high impedance (Hi-Z) state again as shown at (e) in FIG.
3
.
In the conventional semiconductor memory device thus constructed, the specification of RAM prescribes the maximum access times (t
AAC
(max), t
RAS
(max), t
CAS
(max) and others) in connection with the access time. The specification also prescribes the operation conditions of RAM. For example, a prescribed power supply potential is 5V±10% (4.5 V−5.5 V), and a prescribed operation temperature is from 0° C. to 70° C.
The access time of RAM mainly depends on the performance of transistors forming the RAM. In general, a current drive capability of the MOS transistor decreases as the power supply potential decreases, and also decreases as the operation temperature decreases. The operation speed decreases as the current drive capability decreases. The maximum access time is equal to the access time required under the worst environmental conditions of RAM, i.e., at a low power supply potential in a high temperature.
When designing the timing of a system using a conventional RAM, the designed access time must be equal to the maximum access time in view of a margin for allowing use or operation under the worst conditions of a low power supply potential and a high temperature, even if the system will not be used under the worst conditions in practice. Therefore, in spite of the fact that the actual access time can be shorter than the maximum access time unless it is used under the worst conditions, the speed of the system is unduly low due to the timing margin determined in view of the use under the worst conditions.
In a system operating in synchronization with a clock of a fixed frequency, it is necessary to design the system to operate with a low frequency allowing correct operation of the RAM under the worst conditions of the system. In practice, the system may not be used under the worst conditions. Even in such a case that the system can be operated at a higher speed because, e.g., the RAM can be accessed at a higher speed, the system must actually operate at the low speed as if it were operating under the worst conditions due to the fact that the clock frequency is fixed, so that the system speed is unduly reduced.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a semiconductor memory device which can perform a normal operation at an increased speed without changing a manufacturing process as well as a computer provided with the same.
Another object of the invention is to increase an operation speed of a semiconductor memory device and a computer by eliminating undue restriction relating to the operation speed of a system under conditions other than the worst conditions.
Still another object of the invention is to increase an operation speed of a semiconductor memory device and a computer by using data immediately when the data is supplied from the semiconductor memory device under conditions other than the worst conditions.
An additional object of the invention is to provide a semiconductor memory device and a computer allowing a faster operation by increasing a data output speed itself of the semiconductor memory device and by allowing immediate use of the data when the data is output.
A further additional object of the invention is to provide a semiconductor memory device and a computer which can coexist with a conventional system and can perform a conventional operation at a higher speed.
A computer according to the invention includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal applied through an address input terminal to a data output terminal, and being operable to output a data output fixing signal attaining a predetermined level in response to output
Encarnación Yamir
Mitsubishi Denki & Kabushiki Kaisha
Yoo Do Hyun
LandOfFree
Semiconductor memory device and computer having a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and computer having a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and computer having a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2909660