Semiconductor integrated circuit having three wiring layers

Details Semiconductor integrated circuit having three wiring layers Semiconductor integrated circuit having three wiring layers

2000-11-06

2002-05-14

Clark, Jhihan B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S211000, C257S296000, C257S903000, C257S765000

Reexamination Certificate

active

06388329

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a semiconductor integrated circuit comprising first, second and third wiring layers which are successively stacked on a semiconductor device group including a plurality of semiconductor devices having prescribed functions respectively.
2. Description of the Background Art
In relation to a general megabit-class semiconductor memory device, particularly a DRAM (dynamic random access memory), the mainstream is formed by a memory cell array architecture employing two layers of aluminum wires, as described in ESSCIRC Proceeding, September 1991, pp. 21 to 24.
A conventional semiconductor integrated circuit employing such two layers of aluminum wiring patterns is now described with reference to the drawings.
FIG. 13
illustrates the structure on a chip of the conventional semiconductor integrated circuit.
Referring to
FIG. 13
, the semiconductor integrated circuit includes four memory cell array regions
31
which are arranged in two rows and two columns, and a peripheral circuit region
32
which is provided between the four memory cell array regions
31
. Each memory cell array region
31
includes a plurality of subarrays
33
which are arranged in the row direction, a plurality of sense amplifier blocks
34
which are provided between and on both ends of the subarrays
33
, a row decoder
35
which is arranged adjacently to the plurality of subarrays
33
and the plurality of sense amplifier blocks
34
, and a column decoder
36
which is arranged adjacently to the innermost sense amplifier block
34
.
Concrete structures of the subarrays
33
and the sense amplifier blocks
34
shown in
FIG. 13
are now described.
FIG. 14
illustrates the concrete structures of each subarray
33
and the sense amplifier blocks
34
shown in FIG.
13
.
Referring to
FIG. 14
, each subarray
33
includes a plurality of memory cells MC, a plurality of bit lines BL and /BL (″/″stands for complementary signal wires), and a plurality of word lines WL. The subarray
33
has a folded bit line structure.
The memory cells MC are connected with corresponding ones of the bit lines BL and /BL and the word lines WL respectively. The bit lines BL and /BL are connected with sense amplifiers
34
a.
In the conventional DRAM, a plurality of semiconductor devices such as transistors and capacitors are formed on a silicon substrate, and a first high melting point metal wiring layer W, a second aluminum wiring layer Al
1
and a third aluminum wiring layer Al
2
are successively stacked thereon.
In the region shown in
FIG. 14
, the first high melting point metal wiring layer W is employed as the bit lines BL and /BL. The second aluminum wiring layer Al
1
is employed as parts of the word lines WL. In more concrete terms, this layer Al
1
is employed as shunts (pile drivers) for reducing the time constants of the word lines WL. The third aluminum wiring layer Al
2
is employed as column selection lines CSL for transmitting an output signal of each column decoder
36
shown in FIG.
13
.
The bit lines BL and /BL are formed by the high melting point metal wiring layer W as hereinabove described, for the following reason:
It is necessary to reduce power consumption by reducing the capacitances of the bit lines BL and /BL themselves, to ensure operating margins by increasing signal amplitudes read from the memory cells MC, and to reduce noises between the bit lines BL and /BL by reducing the capacitances across the same. Thus, it is necessary to reduce the thicknesses of the bit lines BL and /BL, which in turn tend to be increased in resistance. However, it is necessary to reduce the bit lines BL and /BL in resistance, in order to increase the speed of the DRAM. Therefore, the high melting point metal wiring layer W having a low resistance value is employed for the bit lines BL and /BL, in order to reduce the resistances thereof in addition to reduction in thickness. The high melting point metal wiring layer W is also adapted to prevent the material forming the bit lines BL and /BL from migration into the silicon substrate. While the high melting point metal has generally been prepared from tungsten silicide (WSi), a material having a lower resistance such as tungsten (W) or titanium silicide (TiSi) is recently employed for the purpose of reduction in resistance.
The structure in an area X of the peripheral circuit region
32
shown in
FIG. 13
is now described in detail.
FIG. 15
is an enlarged view showing respective regions on the semiconductor substrate in the area X shown in FIG.
13
.
Referring to
FIG. 15
, the area X of the peripheral circuit region
32
includes bus regions BR, NMOS regions NR and PMOS regions PR. The bus, NMOS and PMOS regions BR, NR and PR are alternately set along the longer edges of the area X respectively.
The bus regions BR are provided thereon with bus wires for transmitting signals from peripheral circuits by the third aluminum wiring layer Al
2
, with no semiconductor devices such as NMOS and PMOS transistors. On the other hand, the NMOS regions NR are provided with NMOS transistors, and the PMOS regions BR are provided with PMOS transistors and the like. The NMOS and PMOS regions NR and PR are hereinafter defined as circuit regions CR.
The structure of the third aluminum wiring layer Al
2
in the area X is now described in detail.
FIG. 16
is an enlarged view showing the structure of the third aluminum wiring layer Al
2
in the area X shown in FIG.
13
.
Referring to
FIG. 16
, a plurality of bus signal wires BSL are arranged in each bus region BR. Two power supply wires V
cc
and V
ss
are arranged in each circuit region CR. The respective wires are thereafter similarly repeated on the respective regions. The bus signal wires BSL and the power supply wires V
cc
and V
ss
are formed by the third aluminum wiring layer Al
2
.
The semiconductor devices which are formed on each circuit region CR are supplied with power supply voltages V
cc
and V
ss
by the set of power supply wires V
cc
and V
ss
. In more concrete terms, the third aluminum wiring layer Al
2
is connected with the second aluminum wiring layer Al
1
via through holes, while the second aluminum wiring layer Al
1
is connected with prescribed semiconductor devices which are formed on the circuit regions CR through contact holes. Namely, the second aluminum wiring layer Al
1
is employed as local wires for connection with the semiconductor devices which are formed on the circuit regions CR. Also on the bus regions BR, the second aluminum wiring layer Al
1
is employed as local wires, for connecting the bus signal wires BSL which are formed by the third aluminum wiring layer Al
2
with prescribed semiconductor elements formed on the circuit regions CR.
In the conventional DRAM, as hereinabove described, the first high melting point metal wiring layer W, which is employed as the bit lines BL and /BL in the memory cell array regions
31
, is hardly used in the peripheral circuit region
32
. This is because the sheet resistance of the conventional high melting point metal wiring layer W which is made of tungsten silicide (WSi) is so high that the signal delay is too large for application to local wires for connecting the semiconductor devices provided on the circuit regions CR with each other.
Therefore, it is necessary to use the second aluminum wiring layer, portions of the third aluminum wiring layer provided on the circuit regions and the remaining portions thereof as the local wires, the power supply wires and the bus signal wires respectively as hereinabove described, and hence it is necessary to provide the bus regions which are provided with no semiconductor devices on the semiconductor substrate, in addition to the circuit regions. Consequently, high integration of the semiconductor integrated circuit cannot be attained.
In recent years, however, it is possible to employ a high melting point metal wiring layer having a small sheet resistance,

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