Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-09-21
2002-07-02
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S715000
Reexamination Certificate
active
06413875
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to temperature sensitive dry etch processes used in semiconductor fabrication and apparatuses for performing dry etches, and more particularly to controlling the temperature of such processes and such apparatuses to maintain selectivity while providing a high etch rate.
The manufacture of semiconductor devices, and particularly multilayer structures, involves, among other fabrication steps, the patterned etching of areas of the semiconductor surface which are not protected by a pattern of photoresist material. Such etching techniques use either liquid (“wet”) etching compositions or gaseous “dry” etching compositions. For example, certain halogen-containing mineral acids such as HCl and HF are known to be active etchants for many of the materials found in semiconductors. When used as wet etchant compositions, these compositions will etch the semiconductor surface isotropically, i.e., in both vertical and lateral directions.
Etching of semiconductor layer materials may also be accomplished using, for example, halogen-containing compounds in the gas phase. Such techniques are broadly categorized as dry etching and include plasma etching, ion beam etching, and reactive ion etching. The use of gas plasma, in the form of gaseous ions, electrons, and neutrals formed from radio frequency discharge, as the etchant provides for substantially anisotropic etching (i.e., etching in the vertical direction only) of the semiconductor surface. Anisotropic etching techniques have become increasingly important as higher density (and thus smaller dimensions) multilayer semiconductors have been introduced.
Such small dimensions and tight tolerances in this industry have created problems which cannot be successfully addressed using photolithography techniques in combination with wet etching. Accordingly, anisotropic etching procedures, in which feature widths must be maintained within certain alignment tolerances, are used. One technique which has been developed along with anisotropic dry etching is the use of etch stop layers.
In an etch stop procedure, an etch stop layer of material is deposited atop an underlying structure. An outer layer, through which desired patterns will be formed, is then deposited over the etch stop layer. The etch stop layer is used to terminate the etching process through the outer layer once that layer has been completely removed in a desired pattern and to protect the underlying structure from the etchant.
Etch stop procedures are designed to have (1) a high outer layer etch rate which (2) etches anisotropically to produce substantially upright sidewalls through the outer layer, and (3) has a high selectivity so that the etchant preferentially etches the material of the outer layer, but not (or only very slowly) the etch stop layer. A preferred etch stop material in the art is silicon nitride because it has properties which are well known and is used widely in semiconductor fabrication. A typical outer layer to be etched comprises silicon dioxide.
One process for obtaining high selectivity in the etching procedure is taught in Blalock et al, U.S. Pat. No. 5,286,344, where a fluorinated etchant containing specific additives is used to form a gas plasma which etches silicon dioxide at a high selectivity with respect to an underlying silicon nitride layer. Other gas plasma etchants with high selectivity are also known.
One problem which has existed in the art for such selective oxide
itride etches is that if the temperature of the substrate to be etched or the interior of the plasma etching apparatus is too high, the rate of oxide etch drops, and the etch may not be completed. That is, a portion of the insulating oxide layer may remain, preventing good electrical connections from being formed in later fabrication steps. Additionally, if the temperature in the plasma etching apparatus is too high, some of the etchant gas may polymerize and be deposited on the walls of the etched layer. The presence of polymer impedes the rate of etch and results in the formation of angled, not vertical, walls. The polymer may also interfere with completion of the etch through to the etch stop layer. Such overheating problems may occur where the outer layer to be etched is relatively thick, or where the etching process must be continued for a relatively long time period such as in a self-aligned contact etch, or where a high electrode temperature is used.
While some plasma etch apparatuses include a wafer cooling system to maintain the wafer at a constant temperature during the etching process, maintaining a constant wafer temperature does not address the overheating problems in the plasma generating apparatus. Accordingly, the need still exists in the art for a technique for improving the performance of a temperature-sensitive etch process.
SUMMARY OF THE INVENTION
The present invention meets that need by controlling the temperature of a dry etch process in a plasma etch chamber to maintain selectivity while also providing a high etch rate by introducing one or more cooling steps into the etch process. The process includes the steps of providing a semiconductor substrate having at least one layer of material thereon to be etched in a chamber and initiating plasma etching of one or more selected areas on the layer of material to be etched in the chamber. To maintain selectivity of the etch as well as a high rate of etch, the formation of plasma is terminated prior to exceeding a predetermined maximum temperature at at least one selected location in the chamber. For example, the location may be a wall of the chamber, any temperature-sensitive hardware within the chamber such as an electrode, or the semiconductor substrate. The temperature at the at least one selected location is then reduced prior to the resumption of plasma flow and etching. This temperature reduction may be accomplished by actively cooling the selected location or simply permitting that location to cool. The plasma etch is then continued. The etch may optionally be terminated again to permit cooling, as needed, until etching has been completed.
In a preferred embodiment of the invention, the layer of material to be etched comprises silicon dioxide which overlies a silicon nitride etch stop layer. In this preferred embodiment, the predetermined maximum temperature for the process is approximately 120° C. Above that temperature, the etch rate of the oxide becomes too low, and polymer formation on the walls of the etched silicon dioxide layer increases.
To insure that the predetermined temperature of the process is not exceeded, the temperature of at least one selected location in the chamber may be monitored. In a preferred embodiment, the temperature of the semiconductor substrate is monitored by a fiber optic probe positioned adjacent the back side of the substrate. A similar probe may also be utilized to monitor the temperature of the electrode and/or the chamber walls.
Generally, simply terminating the flow of plasma to the chamber and pausing for several minutes will cause the temperature to drop sufficiently that the etching process may then be resumed. Alternatively, the chamber may be actively cooled by flowing inert gas through it or by raising the gas pressure in the chamber to increase convective heat transfer from the semiconductor substrate, the electrode, and the walls in the chamber. The semiconductor substrate may be actively cooled by flowing inert gas over the backside thereof.
The present invention is also useful for commercial apparatuses which etch a series of semiconductor wafers in sequence under automated control. The process includes the steps of providing a first semiconductor substrate having at least one layer of material thereon to be etched in a chamber and initiating plasma etching of one or more selected areas on the layer of material to be etched in the chamber and continuing plasma etching thereof until the etch is completed. The first semiconductor substrate is removed and replaced with a succeeding semiconductor substrate to be e
Blalock Guy T.
Howard Bradley J.
Chen Kin-Chan
Killworth, Gottman Hagan & Schaeff, L.L.P.
Micro)n Technology, Inc.
Utech Benjamin L.
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