Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
1999-12-16
2002-08-20
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S773000, C257S778000
Reexamination Certificate
active
06437452
ABSTRACT:
The present application is an application filed in accordance with 35 U.S.C. §119 and claims the benefit of earlier filed Singapore application number 9804800-2 filed on Dec. 17, 1998.
1. Field of the Invention
This invention relates generally to a semiconductor device assembly, and in particular, to a chip assembly which includes a single or multi-layered substrate of which circuitry traces are connected to the input/output terminal pads of the IC chip through deposition of conductive material onto pre-formed leads in substrate via holes.
2. Background of the Invention
Recent developments in semiconductor packaging suggest an increasingly critical role of the technology. New demands are coming from requirements for more leads per chip (and hence smaller input/output terminal pad pitch), shrinking die and package footprints, and higher operational frequencies that generate more heat (thus requiring advanced heat dissipation designs). All of these considerations must be met and, as usual, are placed in addition to the cost that packaging adds to the overall semiconductor manufacturing process.
Conventionally, there are three predominant chip-level connection technologies in use for integrated circuits, namely wire bonding, tape automated bonding (TAB) and flip chip (FC), to electrically or mechanically connect integrated circuits to lead frame or substrate circuitry. Wire bonding has been by far the most broadly applied technique in the semiconductor industry because of its maturity and cost effectiveness. However, this process can be performed only one wire bond at a time between the semiconductor chip's bonding pads and the appropriate interconnect points. Furthermore, because of the ever-increasing operational frequency of the device, the length of the interconnects need to be shorter to minimize inductive noise in power and ground, and also to limit the crosstalk between the signal leads. An example of such a method is disclosed in U.S. Pat. No. 5,397,921 issued to Kanezos.
Flip chip technology is characterized by mounting of an unpackaged semiconductor chip with the active side facing down to an interconnect substrate through some kind of contact anchors such as solder, gold or organic conductive adhesive bumps. The major advantage of the flip chip technology is the short interconnects which can, therefore, handle high speed or high frequency signals. There are essentially no parasitic elements, such as inductance. Not only is the signal propagation delay slashed, but much of the waveform distortion is also eliminated. Flip chip also allows an array interconnecting layout that provides more I/O than a perimeter interconnect with the same die size. Furthermore, it requires minimal mounting area and weight, which results in overall cost savings since no extra packaging and less circuit board space is used. An example of such a method is disclosed in U.S. Pat. No. 5,261,593 issued to Casson et al.
While flip chip technology shows tremendous advantage over wire bonding, its cost and technical limitations are significant. First of all, prior art flip chip technology must confront the challenges of forming protruded contact anchors or bumps to serve as electrical connections between the integrated circuit chip and substrate circuitry. Examples of such an approach are disclosed in U.S. Pat. No. 5,803,340 issued to Yeh, al. et. al. and U.S. Pat No. 5,736,456 issued to Akram. These approaches typically include a very costly vacuum process to deposit an intermediate under-bump layer that serves as an adhesive and diffusion barrier. This barrier layer is typically composed of a film stack that can be in the structure of chromium/copper/gold. Bumping materials such as solder are subsequently deposited onto this intermediate layer through evaporation, sputtering, electroplating, solder jetting or paste printing methods followed by a re-flow step to form the solder contacts. Although evaporation and sputtering techniques can potentially offer high density bumps, these processes need very tight controls and normally result in poor yield. In addition, from the mechanical structural viewpoint, the coefficient of thermal expansion (CTE) of silicon and the substrate may be quite different, causing the stress between these two parts after attachment to build up and become fully loaded onto these bumps. This can then cause severe joint cracking and disconnection problems during normal operation conditions. As a result, a conventional flip chip assembly is not only very costly but also suffers from very serious reliability problems and a high fatality ratio.
Techniques for fabricating the intermediate under-bump barrier layer as well as the bump material utilizing electroless plating are also known in the prior art. An example of such a method is described in the U.S. Pat. No. 5,583,073 issued to Lin et al. Although this electroless technique provides an economical, simple and effective method for providing an under bump barrier layer, contacting material such as solder or adhesive is still required for assembling. Solder dipping or screen printing of solder paste onto these bumps has been explored but have been met with very limited success due to lack of solder bridging control and non-uniform deposition of solder on the metal bump. This process also suffers from poor process control as input/output terminal pad spacing gets smaller. Additional problems have been encountered with tin/lead solder systems due to its increase in electrical resistance over time, and these solder contacts are easily fatigued by thermo-mechanical stressing.
In view of the limitations of currently available integrated circuits assembling methods, a high performance, reliable and economical device and method that can effectively interconnect integrated circuits to the external circuitry would be greatly desirable.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a flip chip assembly to address high density, low cost and high performance requirements of semiconductor packaging. The present invention involves the bonding of substrate circuitry to semiconductor device through connection of pre-formed leads inside the via holes or apertures to IC terminal pads beneath the via holes without the need for conventional bumps, bonding wire, or other media. This provides both electrical and mechanical connections between the IC chip and circuitry of the substrate.
In accordance with an aspect of the invention, a flip chip assembly includes a semiconductor chip including a terminal pad, a substrate including a dielectric layer and an electrically conductive trace, wherein the dielectric layer includes first and second surfaces that are opposite one another and a via hole that extends between the first and second surfaces, the conductive trace is disposed on the first surface and bent proximate to a corner between the first surface and the via hole at a different angle than the corner and extends into the via hole without extending to the second surface and without contacting the terminal pad, the via hole is aligned with the terminal pad, and the second surface is attached to the chip, and a plated metal in the via hole that is plated on and electrically connects the conductive trace and the terminal pad.
Preferably, the conductive trace laterally extends across a majority of a diameter of the via hole and vertically extends across a majority of a depth of the via hole and contacts substantially none of the dielectric layer at sidewalls of the via hole, the plated metal contacts the dielectric layer at sidewalls of the via hole, substantially all of the plated metal is withtin the via hole, and the conductive trace and the plated metal are the only materials in the via hole. Suitable plated metals include electroplated and electrolessly plated metals.
In accordance with another aspect of the invention, rather than the plated metal, a solder joint in the via hole contacts and electrically connects the conductive trace and the terminal pad. The solder joint also contacts some but not al
Clark Sheila V.
Sigmond David M.
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