Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1999-01-28
2002-09-17
Boudreau, Leo (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C250S309000
Reexamination Certificate
active
06453063
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuit imaging and analysis and more particularly to the use of focused ion beams for imaging integrated circuits.
BACKGROUND OF THE INVENTION
In the past, reverse engineering of circuits was a straightforward task. A circuit board was examined for traces providing a series of conductive connections between components. Circuit components were then analysed to determine connected elements and finally, a schematic of the board was entered for improvement, re-layout, or incorporation into a current design.
With the advent of MSI, LSI, and VLSI, this process became far more tedious. Initial attempts at reverse engineering integrated circuits relied on visual images of integrated circuit layers. Overlapping portions of a layer of an integrated circuit were photographed such that a portion of a layer is photographed. The images were developed as photographs and the photographs were assembled by hand in order to overlap adjacent images appropriately. Because of the redundant nature of integrated circuits, assembling the overlapping images into a single large composite image was difficult and required some skill.
Once a composite image was formed by taping or gluing the photographs together in an appropriate fashion, analysis of the images began. The analysis was performed by a person skilled in the art of reverse engineering or integrated circuit fault analysis and includes the steps of determining conductors, transistors, capacitors, resistors, etc. and forming a schematic of the circuit in dependence upon the analysis.
Reverse engineering a complex integrated circuit often represents many man months of effort and requires significant contribution by highly skilled individuals.
With the miniaturisation of integrated circuits, optical wavelengths become less useful for imaging. Current state of the art integrated circuit fabrication facilities work at 0.25-0.35 microns and are expected to be further miniaturised. At sizes smaller than these, optical wavelengths become too large to properly image integrated circuit components. In order to overcome this limitation, it has been proposed to use scanning electron microscope (SEM) devices; however, with the use of scanning electron microscopes, new problems arise. Optical imaging captures information of the outermost opaque surface and optical transmission presents certain known problems. SEM devices image only surface information unless materials of different average atomic number are present within the electron beam penetration depth. The topography that is imaged is the final result of all the processes that produce changes in height at the surface such as oxidation and metallization crossovers. Thus it is difficult to extract information unambiguously relating solely to the upper metallization.
It is therefore common to produce images containing a lot of background information as well as an image of an outermost layer. Many current imaging techniques for reverse engineering focus heavily on techniques for processing the information to extract foreground information for circuit analysis. At present, human analysis is the most effective.
It would be advantageous to automate some of the functions required to reverse engineer or analyse an integrated circuit (IC).
Prior Art
In U.S. Pat. No. 4,623,255 in the name of Suszko and issued on Nov. 18, 1986, a Method of Examining Microcircuit Patterns is disclosed. The method comprises the steps of photographing a portion of an IC with dark field illumination and then developing the photograph. As described above, the mosaic formed by assembling photographs is time consuming and requires expertise.
In U.S. Pat. No. 5,086,477 in the name of Yu et al. and issued on Feb. 4, 1992, an Automated System for Extracting Design and Layout Information from an Integrated Circuit is disclosed. The system comprises an image capture means for capturing a plurality of images of an IC and a computer for assembling the images into a large mosaic by determining image overlap or by extrapolating images to fill gaps between adjacent images. Unfortunately, when working with current IC tolerances, gaps between abutting images may contain important circuit elements. Further the system taught by Yu et al. requires a known element to occur on each of several layers in order to align image composites for a multi-layer IC. A skilled worker identifies the known element. Finding and identifying such an element on each layer of the IC is often time consuming. Also, removing an IC from the imaging system in order to prepare it for imaging successive layers, makes aligning successive layers automatically very difficult.
In U.S. Pat. No. 5,191,213 in the name of Ahmed et al. and issued on Mar. 2, 1993, an Integrated Circuit Structure Analysis method and apparatus are disclosed. An electron beam is directed toward successive layers of an IC. Some known problems with the use of electron beam scanning of IC layers are solved by Ahmed et al. Filtering of image data is required to extract foreground data from background data before analysis is possible. This is a significant problem. Also, removing an IC from the imaging system in order to prepare it for imaging successive layers, makes aligning successive layers in an automatic fashion very difficult.
In U.S. Pat. No. 5,694,481 in the name of Lam et al. and issued Dec. 2, 1997, a system for automatically constructing a mosaic of images using polygon extraction and filtering of images is disclosed. The method appears useful for extracting circuit information from SEM image data. The method disclosed deals mostly with the issues of filtering and mosaicing of filtered images. The step of filtering to extract foreground information from background and foreground information is very time consuming because of the size and resolution of the images captured. It would be advantageous to eliminate this step, but unfortunately, using SEM devices automated circuit extraction is not currently possible absent complex filtering of image data.
Focused ion beam (FIB) systems are known for use in several applications. FIBS are useful in micromachining, imaging and etching. The use of FIBS in imaging is well documented. In imaging, an ion beam is focused toward a location and backscattered ions are detected. Other particle emissions caused by collisions between ions within the beam and a surface being imaged are also detected. Analysis of the detected particles results in an image. FIB systems are also used in etching. Etching with FIBS began with applications for cutting traces in integrated circuits to allow for IC repair. With gas assisted etching, FIB systems provide a convenient system for etching away selected material from a surface of an IC in order to form holes of a desired depth.
Gas assisted etching is performed as follows. A reactive gas such as chlorine is fed into the FIBS near a surface of a substrate. The gas adsorbs to the surface approximating a monolayer. When the surface is scanned with ion beams, the energy of the ion beams is used to break chemical bonds, thus causing chemical reactions to proceed. As well as providing the energy needed to break bonds, the ions supply momentum to sputter the substrate. The chemical etching helps to enhance the physical sputtering of the ion beam. Another benefit is that the sputtered particles are volatilised and pumped away by a vacuum system forming part of the FIBS.
Use of correct etchant gas significantly increases etching rate over FIB etching without an etchant gas. The increased etching rate is material dependent so selection of a gas for a particular material results in improved etching performance and improved control because of etching rate decreases when different material is exposed. These two advantages to gas assisted etching are known to allow etching of deep narrow holes.
In U.S. Pat. No. 5,561,293 in the name of Peng et al. and issued on Oct. 1, 1996, a Method of Failure Analysis with CAD Layout Navigation and FIB/SEM Inspection is disclosed. The method incorporates a du
Breton Pierrette
Elvidge Julia
Haythornthwaite Ray
James Dick
Ludlow Terry
(Ogilvy Renault)
Boudreau Leo
Chipworks
Patel Kanji
Wood Max R.
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