Read-out circuit

Details Read-out circuit Read-out circuit

2001-08-30

2002-07-30

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

C365S203000, C365S205000, C365S145000

Reexamination Certificate

active

06426906

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a read-out circuit in a ferroelectricity memory.
The publication “FRAM IC Card Technology” (Hidemi Takasu and Toshinori Takuma, published by: Science Forum, 1999, p.p. 35~40) explains the basic operation of a 1T-1C (one transistor-one ferroelectric capacitor) type ferroelectricity (FeRAM) and clarifies the problems arising therein.
DESCRIPTION OF THE RELATED ART
It has been noted that a reference potential generating cell (also referred to as a dummy memory cell), which is accessed more frequently compared to data memory cells, quickly becomes degraded to result in the reduction in the degree of change in the electrical charge occurring during a polarization inversion and a lower reference potential.
When a 1T-1C type FRAM is used to constitute a reference potential generating cell, too, the reference potential generating cell which is accessed more frequently than data memory cells becomes degraded readily, resulting in a reduction in the degree of change in the electrical charge occurring during a polarization inversion and a lower reference potential, as described above. Thus, a problem in that an erroneous read-out tends to occur readily arises.
In addition, while the publication mentions a 2T-2C type FRAM as a means for improving the reliability, it also asserts that since its memory cell array area is almost double the memory cell array area of the 1T-1C FRAM, its use will become extremely limited as further miniaturization is pursued in the future.
The main object of the present invention, which has been completed by addressing the problem of read-out circuits in the prior art, is to provide a new and improved read-out circuit through which the reliability of the reference potential generating cell is improved while utilizing a 1T-1C type FRAM with a smaller area to constitute the reference potential generating cell.
SUMMARY OF THE INVENTION
In order to achieve the object described above, the read-out circuit according to the present invention that amplifies a binary signal through a sense amplifier and reads out the amplified signal as a bit line potential is provided with a potential setting circuit that resets the signal corresponding to the lower potential in the binary signal to a given potential, at a stage preceding the stage at which the sense amplifier is provided. It is to be noted that the potential setting circuit may reset the lower potential signal to a potential near 0 V.
By adopting this structure in which a constant potential can be used as the reference potential, stable operation is realized. In addition, since a constant potential is used as the reference potential, the degree of change occurring over time can be reduced. Furthermore, since the reference potential line is not required to have a large capacity, the power consumption during a read-out operation can be reduced.
It is desirable that the potential setting circuit include a transistor the substrate potential of which can be set freely and that the operating point of the potential setting circuit can be adjusted via the transistor substrate potential. When such a structure is adopted, the operating point can be adjusted in conformance to the characteristics of the ferroelectric capacitor when the process is completed. As a result, the operating point of the potential setting circuit can be set freely for a specific use.
In addition, it is desirable that the potential setting circuit include a transistor and another transistor that is provided to forcibly discharge the charge stored at the gate of the first transistor. In such a structure, the electrical charge stored at the gate of the first transistor is forcibly discharged even during a high-speed operation, eliminating any residual charge at the gate, to enable stable operation.
Moreover, the read-out circuit according to the present invention that amplifies a binary signal through a sense amplifier and reads out the amplified signal as a bit line potential, having, a potential setting circuit that resets a lower potential signal in the binary signal to a given potential, provided at a stage preceding the sense amplifier, wherein, the potential setting circuit includes, a first transistor having a gate thereof connected to a bit line, which is turned on when the potential generated at the bit line is equal to or lower than a specific threshold voltage, and a second transistor which is turned on in response to the first transistor entering an ON state and resets the potential at the bit line to a given potential is provided.


REFERENCES:
patent: 5978250 (1999-11-01), Chung et al.
patent: 6144601 (2000-11-01), Takeda
FRAM Inc. Card Gijutsu (FRAM IC Card Technology) PP35-40, 1999.

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