Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-15
2002-06-25
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S384000, C257S396000, C257S408000, C257S412000, C257S413000
Reexamination Certificate
active
06410967
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to fabricating a transistor having a metal silicide formed in close proximity to the gate. This invention also relates to fabricating a transistor having a metal gate electrode.
2. Description of the Related Art
Early MOS integrated circuits were developed using aluminum gate electrodes. These early MOS transistors, however, had several disadvantages. For example, because the earliest MOS circuits utilized p-channel devices, they required a power supply of −12 V for the drain supply. They were also very slow, about an order of magnitude slower than bipolar devices. Although the use of n-channel devices could have provided significantly improved performance, only depletion-mode NMOS devices could be reliably manufactured, whereas enhancement-mode NMOS devices are required for most applications.
In addition, aluminum must be deposited following completion of all high-temperature processing steps, including implantation and subsequent anneal of the source and drain regions. This requires separately aligning the aluminum gate electrode to the source and the drain. If the gate does not fully extend between the source and drain regions, the device will not operate. As such, aluminum gates were formed with some degree of overlap of the source and the drain to allow for variability in lateral diffusion of the source and drain and for possible misalignment of the gate during fabrication. Overlap of the gate with the source and drain regions, however, can be a particularly troublesome source of stray capacitance. Parasitic capacitances associated with MOS devices can limit the high-frequency operation of MOS transistors.
One of the key process innovations for MOS integrated circuit fabrication was the replacement of aluminum with heavily doped polycrystalline silicon (“polysilicon”) as the gate electrode. Because polysilicon, like the silicon substrate upon which integrated circuits are typically formed, has a high melting point, the gate electrode may be formed prior to the source and drain regions. Subsequent high-temperature anneals may then be used to drive in the source and drain implants and repair damage to the substrate without adversely affecting the gate. Forming the source and drain regions self-aligned with the gate also decreases overlap, and thus parasitic capacitance. The self-aligned process also advantageously allows for increased packing density of transistors upon the substrate and simplifies the fabrication procedure.
The use of polysilicon as the gate conductor is not, however, without its own disadvantages. Because polysilicon is a semiconductive or insulative material, it must be doped with conductive impurities to decrease its resistivity. However, even when doped at the highest practical concentrations, polysilicon has a sheet resistance about 400 times higher than the sheet resistance of an aluminum layer of comparable thickness. Further, polysilicon gate electrodes are subject to the so-called “poly depletion effect.” That is, dopants implanted into the polysilicon gate to render it conductive do not penetrate completely to the interface between the polysilicon and the underlying gate conductor. The magnitude of the poly depletion effect can vary, but in general at least 3-10% of the polysilicon remains undoped. As a result, the undoped portion of the gate electrode acts as an insulator, increasing the effective thickness of the gate dielectric and thus the threshold voltage.
High resistance values in polysilicon interconnect lines can lead to long propagation delays and severe variations in DC voltages within an integrated circuit. The formation of metal silicide layers on top of the doped polysilicon (“polycide” layers) was developed to at least partially overcome this disadvantage. Polycide layers have resistivities on the order of 20 times lower than the resistivity of polysilicon. Further, silicide layers may be formed upon the upper surfaces of the source and drain areas in order to minimize the contact resistance in submicron MOSFETs.
Contact holes or vias may be formed in an interlevel dielectric covering a semiconductor topography to expose a portion of the upper surface of the silicon substrate. The surface of the substrate may be cleaned to remove the thin native oxide layer that forms on silicon surfaces exposed to oxygen-containing ambients. A metal film may then be deposited within the contact holes upon the exposed upper surfaces of the source and drain regions of the silicon substrate. A thermal anneal may be used to cause reaction between the metal and the silicon to form the corresponding metal silicide at the contact. The silicide contact regions are, however, spaced from the gate by at least several hundred angstroms. Thus, although the contact between the metal and the substrate exhibits lowered resistivity due to the presence of the silicide, the spacing of the silicide contact region from the channel contributes to increased resistance, and thus decreased transistor speed, due to the increased conductive path length through the higher-resistivity source and drain regions.
It would therefore be desirable to fabricate a transistor having a gate that combined the low resistivity of metals with the alignment properties of polysilicon. It would further be desirable to fabricate a transistor having metal suicides formed in close proximity to the gate to decrease the resistivity associated with the source-to-drain conductive pathway.
SUMMARY OF THE INVENTION
The problems outlined above may be solved by the technique hereof for forming a transistor having a metal gate electrode and silicide regions formed in close proximity to the gate. According to the process of the present application, the upper surface of a silicon semiconductor substrate may be cleaned using, for example, the well-known RCA method. The RCA method is described in S. Wolf and R. N. Tauber,
Silicon Processing for the VLSI Era, Vol
1
—Process Technology,
pp. 516-518 (Lattice Press, Sunset Beach, Calif.; 1986), which is incorporated herein by reference. A layer of metal is then deposited across the semiconductor substrate. Preferably , the metal is cobalt. Alternatively, the metal may be, e.g., titanium or nickel.
A layer of masking material is deposited across the metal and selectively patterned and etched to form masking structures. The masking material may be a dielectric material, such as silicon dioxide or silicon nitride or a combination thereof or any other suitable masking material(s). In one embodiment, the masking material may be photoresist. Following etching of the masking material, portions of the metal layer not covered by the masking structures are removed from upon the semiconductor substrate. If the masking structures include a dielectric material such as silicon dioxide, either a wet etch or a dry plasma) etch may be used. If the masking structures include photoresist, a plasma etch is preferred to avoid lifting of the photoresist.
In an embodiment, a conformal dielectric material may be deposited across the masking structures and the exposed upper surface of the semiconductor substrate. The dielectric may be, e.g., silicon dioxide (“oxide”), silicon nitride (“nitride”), or silicon oxynitride (“oxynitride”). The dielectric material is preferably deposited to a thickness of less than about 50 angstroms and preferably between about 15 angstroms and about 25 angstroms. In an embodiment, the dielectric layer may be of substantially similar thickness adjacent sidewall surfaces of the masking structures and adjacent the upper surface of the silicon substrate. In an alternative embodiment, the thickness of the dielectric layer may vary such that, e.g., the dielectric layer is thicker adjacent the substrate upper surface than adjacent the sidewall surfaces.
A layer of conductive material may then be deposited upon the dielectric layer. Preferably, the conductive material may be a second metal layer and may include a refractory
Gardner Mark I.
Hause Frederick N.
May Charles E.
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Kowert Robert C.
Wojciechowicz Edward
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