Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-05-11
2002-08-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S228000
Reexamination Certificate
active
06440827
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating a semiconductor component having a wiring that runs piecewise in the substrate, and also a semiconductor component that can be fabricated by this method. Semiconductor components having wirings which run partly in the substrate are disclosed for example in Published, Non-Prosecuted German Patent Application DE 35 02 713 A1 and in German Patent DT 16 14 250 B2.
Integrated circuits, in particular CMOS circuits, are fabricated by a multiplicity of process steps. In this case, the fabrication costs of the circuits are determined by the process complexity and the physical processing time. Highly complex modules often require several hundred individual process steps and many days for the process cycle of the product.
In this case, some of the process steps must be used for producing the wiring that connects the individual active components to one another or ensures the connection of the integrated circuit to the “outside world”. Usually, such connections are realized by one or more interconnect planes made of aluminum.
There are applications, however, in which an interconnect plane made of aluminum is too expensive and requires too much space. Furthermore, integrated circuits realized with an aluminum wiring are not sufficiently protected against external manipulation or the subsequent analysis of a circuit.
In order to be able to perform manipulations on an integrated circuit, as a rule it is necessary to analyze the integrated circuit. To that end, a passivation layer and/or the insulation layers between the wiring planes have to be stripped off layer by layer in order that the wiring planes thus uncovered can be examined. If the wiring planes are present as aluminum wiring, then a circuit analysis of this type can be carried out in a relatively simple manner.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a semiconductor component having a wiring which runs piecewise in the substrate, and also a semiconductor component which can be fabricated by the method that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, in which the analysis of the integrated circuit and also the subsequent manipulation thereof are made significantly more difficult. Furthermore, the method for producing such a wiring should be adapted as well as possible to the method for fabricating the transistors and require as few additional process steps as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a semiconductor component and the method being adapted from a further method for fabricating at least two MOS transistor types. The method includes providing a semiconductor substrate having at least one first zone of a second conductivity type for transistors of a first transistor type and a second zone of a first conductivity type for transistors of a second transistor type. A first insulating layer is applied to the semiconductor substrate. A first dopant of the first conductivity type is introduced into the first zone in a first region of a crossover point between a yet to be formed first conductive connection running in the semiconductor substrate and a yet to be formed second conductive connection running on the semiconductor substrate. A second dopant of the second conductivity type is introduced into the second zone in a second region of a crossover point between the yet to be formed first conductive connection and a yet to be formed third conductive connection running on the semiconductor substrate. A conductive layer is applied to the first insulating layer from which the second conductive connection and the third conductive connection are to be formed from. A first mask is applied using a phototechnology process. The first mask covers the second zone substantailly completely and, in the first zone covers only gate tracks of the transistors of the first transistor type that are to be produced and also an area of the conductive layer forming the second conductive connection running on the semiconductor substrate. The first mask is used for fully removing first areas of the conductive layer or removing only some of the conductive layer in the first areas forming first partially remaining areas functioning as an insulation layer. At least one third dopant of the first conductivity type is introduced into the semiconductor substrate. A second mask is applied using the phototechnology process. The second mask covers the first zone substantially completely and, in the second zone covers only gate tracks of the transistors of the second transistor type that are to be produced and parts of the conductive layer forming the third conductive connection running on the semiconductor substrate. The second mask is used for fully removing second areas of the conductive layer or partially removing some of the conductive layer in the second areas forming second partially remaining areas functioning as an addition part of the insulation layer. At least one fourth dopant of the second conductivity type is introduced into the semiconductor substrate. A temperature is increased so that the first conductive connection running in the semiconductor substrate is formed by regions impregnated by the first dopant, the second dopant, the third dopant and the fourth dopant. The first conductive connection, the second conductive connection and the third conductive connection define wiring running in and on the semiconductor substrate.
The method steps need not necessarily be carried out in the order specified; in particular, the order of the second and third and fourth steps can also be interchanged. With the semiconductor component according to the invention that is fabricated in this way, it is possible to realize low-resistance underpasses below the gate plane, as a result of which a subsequent circuit analysis is made significantly more difficult. The semiconductor component according to the invention thus enables applications in which high security against external manipulations is important.
The method according to the invention furthermore has the advantage that, for producing at least two transistor types, for example PMOS and NMOS transistors, and also the wiring running in the substrate, it only requires three photoplanes, whereas the conventional fabrication methods usually require six or more photoplanes. In the case of the method according to the invention, the masks produced using the phototechnology process serve, in the respective zone, both for patterning the gate tracks or the connections running on the substrate and for introducing the dopant in order to produce the source/drain zones or the connections running in the substrate. By virtue of the saving of three photoplanes, the process sequence is in turn significantly simplified and accelerated, so that cost-effective production can be ensured. Integrated circuits of this type can thus likewise be used in applications in which low fabrication costs, in particular, are important.
In the case of the method according to the invention, it is particularly preferred if a region (or regions) which is (are) not covered by both masks is provided between the first and second zones. This ensures that, in the plane of the conductive layer, only the connections actually provided produce a conductive connection between the first and second zones.
Furthermore, it is preferred if a protective layer, in particular an oxide-nitride-oxide layer, is applied to the conductive layer and is removed after the application of the masks in accordance with the masks.
Likewise, it is preferred if the conductive layer is a polysilicon layer.
In accordance with one embodiment of the present invention, the polysilicon layer is converted by oxidation into the second insulating layer. In this case, it is particularly preferred if the polysilicon layer is converted into the second insulating layer by part of th
Braun Helga
Kakoschke Ronald
Kux Andreas
Plasa Gunther
Stokan Regina
Infineon - Technologies AG
Lattin Christopher
Niebling John F.
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