Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-29
2002-06-18
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S298000, C257S310000, C257S311000
Reexamination Certificate
active
06407419
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a capacitor electrode structure used in a semiconductor memory device and manufacturing method thereof.
2. Description of the Background Art
Generally, a precious metal such as Pt, Ru or Ir or an oxide thereof is used for a lower electrode of a high dielectric capacitor of a semiconductor memory device. Electrical connection between the capacitor lower electrode and the semiconductor substrate is attained by forming a conducting plug formed of an impurity-doped polycrystalline silicon (polysilicon) therebetween, or alternatively, in order to ensure conduction with the conducting plug, by forming a barrier metal layer containing, as a main component, a refractory metal or metal having high melting point, such as Ti, Ta or W on a lower surface of the capacitor lower electrode.
FIG. 35
represents a conventional semiconductor device including a high dielectric capacitor. The semiconductor device includes an isolating insulating film
502
and an active region
503
at a main surface of a semiconductor substrate
501
and connected to other circuit portions by a word line
504
and a bit line
505
. These portions are covered by an interlayer insulating film
506
to prevent a short-circuit. On active region
503
, a conducting plug
507
is formed filling a contact hole penetrating through interlayer insulating film
506
, and on conducting plug
507
, capacitor lower electrode
528
is formed, as described above. On capacitor lower electrode
528
and interlayer insulating film
506
, a capacitor dielectric
511
is formed and a capacitor upper electrode
512
is further formed thereon, providing a capacitor.
In the above described semiconductor device including the high dielectric capacitor, along with the increase in the degree of integration, the area of the capacitor lower electrode has been so reduced as to cause problems which cannot be addressed by the present lithography precision. More specifically, the upper surface of the conducting plug comes to be not fully covered by the capacitor lower electrode. In such a case, the capacitor dielectric and the conducting plug may unavoidably contact with each other or, even when not brought into contact, the dielectric and the conducting plug may be positioned to close to each other. In the following description, the expression that the upper surface of the conducting plug and the capacitor dielectric “contact with each other” refers to an actual contact as well as an arrangement in which the upper surface and the capacitor dielectric are positioned very close to each other though not in actual contact.
Generally, the conductive material for forming conducting plug
507
has, though slightly, a reducing property, as it contains a metal nitride as a main component. The high dielectric material used for capacitor dielectric
511
involves an oxide of Ba, Sr, Ti, Bi, Pb, Zr or the like.
When the capacitor dielectric
511
and conducting plug
507
contact with each other as mentioned above, a chemical reaction between the material of the conducting plug and the material of the capacitor insulator is induced near an interface therebetween during the step of heating. More specifically, the oxide forming the capacitor dielectric is reduced by the metal nitride forming the conducting plug, resulting in oxygen depleted region in the oxide. This means that a region
600
having poor insulation is formed in the capacitor dielectric, and therefore the insulation characteristic of the capacitor degrades (FIG.
35
). Degraded insulation characteristic leads to leakage of charges stored in the capacitor, possibly causing defects in memory retention of the semiconductor memory device. Further, capacitor capacitance decreases and controllability of the capacitor electrode degrades.
When the capacitor dielectric and the conducting plug are in contact with each other or very close to each other, an end portion of the upper surface of the conducting plug has a portion not covered by the capacitor lower electrode but exposed, or a portion not yet but about to be exposed, positioned very close to an outer peripheral line on the lower surface of the capacitor lower electrode, in the manufacturing step where the capacitor lower electrode is formed during manufacturing the semiconductor device. Therefore, in the following description, the situation in which an end portion of the upper surface of the conducting plug “contacts” the capacitor dielectric and a situation in which the end portion of the upper surface is “positioned very close” to the capacitor dielectric, though not actually, in contact also refer to the situation where the end portion is respectively “exposed” and “almost exposed”, and the situation where the end portion is “exposed” also includes a situation where the upper surface of the conducting plug and the capacitor dielectric are “very close”, unless indicated otherwise.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device in which the capacitor dielectric and the conducting plug are separated from each other by such a distance that prevents chemical reaction therebetween even when the end portion of an upper surface of the conducting plug is exposed because of misregistration in lithography, and to provide a manufacturing method thereof.
According to a first aspect, the present invention provides a semiconductor device including an interlayer insulating film formed on a main surface of a semiconductor substrate, a conducting plug formed in a contact hole penetrating through the interlayer insulating film, a capacitor lower electrode formed on the conducting plug and on the interlayer insulating film, and a capacitor dielectric formed to cover the capacitor lower electrode and the interlayer insulating film, wherein an end portion on the upper surface of the conducting plug which is closer to a sidewall of the capacitor lower electrode has a portion overlapping the vicinity of an outer periphery of an upper surface of the capacitor lower electrode when viewed two-dimensionally, and a chemically inactive member is formed in the vicinity of the end portion of the upper surface of the conducting plug between and separating the end portion of the conducting plug and the capacitor dielectric.
In the specification, the “chemically inactive material” forming the chemically inactive member refers to an insulator such as an oxide or a nitride or a precious metal (precious metal of a single element such as Pt, an alloy of precious metals such as PtIr, an alloy of a precious metal and a metal, a precious metal containing O or the like, a compound of the precious metal containing O or the like, or a mixture of the precious metal and the compound such as PtOx, a mixture of Pt and PtO
2
or the like).
As described above, when a chemically inactive material is formed in the vicinity of an end portion having the overlapping portion at the upper surface of the conductive plug, the capacitor dielectric and the conducting plug can be separated from each other with a sufficient distance therebetween. Therefore, there is no possibility of chemical reaction between the capacitor dielectric and the conducting plug, and superior insulation characteristic of the capacitor dielectric is ensured. Therefore, during the operation of the semiconductor device in accordance with the present invention, stored charges are never leaked, and memory retention is surely maintained. Further, decrease in capacitor capacitance or degraded controllability of the capacitor are not experienced. Here, “vicinity of an end portion” encompasses the end portion itself and its periphery.
In the semiconductor device in accordance with the first aspect described above, in some cases where miniaturization proceeds exceeding the lithography precision, the above described end portion at the upper surface of the conducting plug has a portion extended out from an outer periphery
Chaudhuri Olik
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Rao Shrinivas H.
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2906865