Semiconductor logic circuit device of low current consumption

Details Semiconductor logic circuit device of low current consumption Semiconductor logic circuit device of low current consumption

1999-07-19

2002-08-13

Phan, Trong (Department: 2818)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S096000, C326S113000

Reexamination Certificate

active

06433586

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly, it relates to a logic circuit device logically processing an input signal. More specifically, the present invention relates to a semiconductor logic circuit device correctly operating at a high speed under a low power supply voltage.
2. Description of the Background Art
In a recent large scale integrated circuit, a MOS transistor (insulated gate field effect transistor) of a component thereof is reduced in size. In order to guarantee breakdown voltage of the miniaturized MOS transistor, an operating power supply voltage is lowered. Further, the quantity of a charge/discharge current on a signal line is reduced due to the lowering of the operating power supply voltage, thereby reducing current consumption. In addition, the amplitude of an internal signal is also reduced, whereby the signal can be transmitted at a high speed to implement a high-speed operation.
When the operating power supply voltage is lowered, the MOS transistor is reduced in size and a gate insulator film is correspondingly reduced in thickness. The MOS transistor is generally reduced in size in accordance with a rule called a scaling rule. As regards a threshold voltage of the MOS transistor, however, the absolute value thereof cannot be reduced in accordance with the scaling rule together with reduction of the operating power supply voltage. The threshold voltage is a gate-to-source voltage feeding a predetermined drain current with the channel width predetermined. Even if the gate-to-source voltage Vgs is 0 V, a subthreshold current flows. This subthreshold current increases as the absolute value of the threshold voltage decreases. When the absolute value of the threshold voltage of the MOS transistor is decreased in proportion to the reduction of the power supply voltage, therefore, the subthreshold current increases to disadvantageously increase current consumption in a standby state.
In order to solve such a problem of the subthreshold leakage current, a leakage current prevention circuit called a hierarchical power supply, for example, has been proposed.
FIG. 26
illustrates the structure of a conventional semiconductor device having a hierarchical power supply structure. Referring to
FIG. 26
, the conventional semiconductor device includes a main power supply line
1000
transmitting a power supply voltage VCC, a main ground line
1002
transmitting a ground voltage GND, a sub power supply line
1004
coupled to the main power supply line
1000
through a switching transistor
1003
, and a sub ground line
1006
coupled to the main ground line
1002
through a switching transistor
1005
. The switching transistor
1003
is rendered conductive when an active cycle defining signal ZACT is active (low level), while the switching transistor
1005
is rendered conductive when an active cycle defining signal ACT is at a high level of an active state.
The semiconductor device further includes two stages of cascaded inverters
1010
and
1012
as logic circuits. Each of the inverters
1010
and
1012
, which are identical in structure to each other, includes a p-channel MOS transistor PTa and an n-channel MOS transistor NTa. An input signal IN for the inverter
1010
is set low in a standby cycle (both active cycle defining signals ZACT and ACT are inactive). In the inverter
1010
, the source of the p-channel MOS transistor PTa is coupled to the main power supply line
1000
while the source of the n-channel MOS transistor NTa is coupled to the sub ground line
1006
. The inverter
1012
receives the voltages on the sub power supply line
1004
and the main ground line
1002
as operating power supply voltages. In such an active cycle that the input signal IN changes, the active cycle defining signals ZACT and ACT are active, the switching transistors
1003
and
1005
are rendered conductive, the sub power supply line
1004
is coupled to the main power supply line
1000
, and the sub ground line
1006
is coupled to the main ground line
1002
. Therefore, the voltage on the sub power supply line
1004
reaches the level of the power supply voltage VCC, and the voltage on the sub ground line
1006
reaches the level of the ground voltage GND. When the absolute values of the threshold voltages of MOS transistors PTa and NTa are decreased, the inverters
1010
and
1012
operate at a high speed to output output signals in response to the input signal IN.
In the standby cycle, the input signal IN is fixed at a low level and the output signal of the inverter
1010
is fixed at a high level. In this standby cycle, the active cycle defining signals ZACT and ACT are inactivated and hence the switching transistors
1003
and
1005
are rendered non-conductive. In the inverter
1010
, the p-channel MOS transistor PTa is rendered conductive and the voltages of both the source and the drain thereof reach the level of the power supply voltage VCC. In the p-channel MOS transistor PTa, therefore, the source and drain voltages thereof reach the same voltage level to cause no leakage current. In the n-channel MOS transistor NTa of the inverter
1010
, on the other hand, the gate voltage thereof is set low by the input signal IN to cause a subthreshold leakage current. At this time, the voltage level of the sub ground line
1006
rises beyond the ground voltage GND due to the leakage current. The gate-to-source voltage of the n-channel MOS transistor NTa of the inverter
1010
is set in a reverse bias state (the source voltage is higher than the gate voltage), to suppress the subthreshold leakage current.
In the inverter
1012
, on the other hand, an input signal thereto is at a high level. Therefore, the p-channel MOS transistor in the inverter
1012
is rendered non-conductive to be likely to cause a leakage current (subthreshold current). However, the voltage on the sub power supply line
1004
drops below the power supply voltage VCC due to the leakage current. Also in the inverter
1012
, therefore, the gate-to-source voltage of the p-channel MOS transistor is set in a reverse bias state to reduce the subthreshold current.
In the hierarchical power supply structure shown in
FIG. 26
, the connection manner of its power supply nodes is determined depending on the voltage level of the input signal or the output signal in the standby cycle. In this hierarchical power supply structure, therefore, connection of the power supply nodes of logic gates (inverters) can be determined if the logical level of the input signal or the output signal in the standby cycle can be predetermined. If the logical level of the input signal or the output signal in the standby cycle cannot be predicted as in random logic or the like, however, the connection path for the power supply nodes cannot be determined.
FIG. 27
illustrates an exemplary conventional random logic device. Referring to
FIG. 27
, this random logic device includes a drive circuit
1020
buffering input signals, a transfer circuit
1022
latching and transferring output signals of the drive circuit
1020
in synchronization with a clock signal, a logic circuit
1024
performing prescribed logical processing on output signals of the transfer circuit
1022
, a transfer circuit
1026
latching and transferring output signals of the logic circuit
1024
in synchronization with the clock signal, a logic circuit
1028
performing prescribed logical processing on output signals of the transfer circuit
1026
, and a transfer circuit
1030
transferring output signals of the logic circuit
1028
in synchronization with the clock signal.
The drive circuit
1020
includes drivers DR provided in correspondence to the input signals, respectively. The transfer circuit
1022
includes flip-flops F/F provided in correspondence to the drivers DR of the drive circuit
1020
respectively. The logic circuit
1024
includes logic elements GL
1
to GL
3
. . . . Output signals from the flip-flops F/F of the transfer circuit
1023
are transferred to the lo

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