Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2000-11-16
2002-06-25
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S313000, C438S322000
Reexamination Certificate
active
06410395
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising bipolar transistors, in which method, in succession, a first semiconductor layer of monocrystalline silicon, a second semiconductor layer of monocrystalline silicon with 5 to 25 at. % germanium and a third semiconductor layer of monocrystalline silicon are provided on a surface of a silicon wafer by means of epitaxial deposition, base zones of the transistors being formed in the second semiconductor layer of monocrystalline silicon with germanium.
Said three semiconductor layers, i.e. including the second semiconductor layer of monocrystalline silicon to which 5 to 25 at. % germanium is added (Si
1−x
Ge
x
where 0.05 <×<0.20), can be deposited by means of customary MBE (Molecular Beam Epitaxy) or CVD (Chemical Vapor Deposition) processes. The addition of germanium to silicon results in the formation of a semiconductor material having a smaller band gap than silicon. The use of transitions between semiconductor zones having different band gaps enables heterojunction-bipolar transistors (HBTs) to be realized, which are particularly suited for processing signals of a very high frequency, such as signals used in systems for wireless communication.
The addition of germanium to silicon does not only result in a semiconductor material having a smaller band gap than silicon, but also in a semiconductor material having a greater lattice constant than silicon. The deposition of the second semiconductor layer leads, in the course of this deposition process, to the development of mechanical stresses in this semiconductor layer. The size of these stresses depends upon the thickness of the deposited semiconductor layer. The thicker the semiconductor layer, the greater the stresses are. Above a critical thickness, the size of these stresses increases so much that dislocations are formed in the semiconductor layer. As a result thereof, the stresses decrease, however, the semiconductor layer has become useless. Such dislocations may also occur in a semiconductor layer which is thinner than the critical thickness but which is subjected to treatments at high temperatures. Therefore, such treatments should be precluded as much as possible. Dependent upon the quantity of germanium in the semiconductor layer, said critical thickness lies in the range between 10 and 120 nm (10 nm at 25 at. % germanium to 120 nm at 5 at. % germanium). In practice, in the manufacture of HBTs, a layer of a semiconductor material of monocrystalline silicon with germanium is used in a thickness below said critical thickness.
EP 0 551 185 discloses a method of the type mentioned in the opening paragraph, wherein, in a first process step, the first semiconductor layer of monocrystalline silicon is deposited on the surface of the silicon wafer. Areas of field oxide are subsequently formed n this first semiconductor layer by local oxidation of silicon. Next, in a second process step, the second and the third semiconductor layers are deposited. On field oxideenclosed active regions of the first layer, the second and the third layer are deposited in an epitaxial monocrystalline manner, while they are deposited in a polycrystalline manner on the areas of field oxide. The three semiconductor layers are thus deposited in two separate process steps. The second semiconductor layer of silicon contains 10 at. % germanium and is deposited in a thickness of 30 nm. The second semiconductor layer is deposited with a p-type base doping of boron having a doping concentration of 2.10
19
atoms per cc.
EP 0 607 836 also discloses a method of the type mentioned in the opening paragraph, wherein the three semiconductor layers are deposited on the surface of the silicon wafer in a continuous process. Only after the bipolar transistor has been formed in the three semiconductor layers, field-isolation areas are formed by etching grooves and by subsequently filling them with an insulating material. The second semiconductor layer of silicon contains 20 at. % germanium and is deposited in a thickness of 50 nm. The second semiconductor layer is deposited with a p-type base doping of boron having a doping concentration of 1.10
19
atoms per cc.
In both known methods, the second semiconductor layer of silicon to which germanium is added is provided with a base doping of boron during the deposition process. After the deposition of the layers, they are subjected as little as possible to treatments at a high temperature, so that diffusion of boron from the semiconductor layer is precluded as much as possible. In this manner, sharp doping profiles for the base zone are obtained.
A drawback of the two known methods resides in that, owing to the relatively high p-type doping with a concentration of 1.10
19
atoms per cc, the second semiconductor layer can only be used as a base zone for an npn-transistor (a transistor with an n-type doped emitter zone, a p-type doped base zone and an n-type doped collector zone). It is not possible to form a base zone for a pnp-transistor (a transistor with a p-type doped emitter zone, an n-type doped base zone and a p-type doped collector zone) in the second semiconductor layer. To realize an n-type base zone, said high p-type doping would have to be redopedso as to obtain an n-type doping with a doping concentration equal to or below that of the p-type base zone by adding an n-type dopant. This is impossible. As a result, both said methods cannot suitably be used to manufacture circuits comprising both types of transistors in a simple manner.
SUMMARY OF THE INVENTION
It is an object of the invention to provide inter alia a method which enables integrated circuits to be manufactured which comprise bipolar HBT transistors of the npn-type as well as the pnp-type.
To achieve this, the method mentioned in the opening paragraph is characterized, in accordance with the invention, in that the second semiconductor layer of monocrystalline silicon with 5 to 25 at. % germanium is deposited without a base doping, and this base doping is introduced into this second semiconductor layer at a later stage.
The desired base doping can be brought about in a customary manner by ion implantation or by a VPD (Vapor Phase Doping) process. In a VPD process, atoms from a vapor of a dopant (such as phosphine or diborane) are introduced into the semiconductor layers by diffusion. The second semiconductor layer of silicon with germanium can thus be provided with both an n-type and a p-type base doping. As a result, npn-transistors and pnp-transistors can be made side by side in the three semiconductor layers. The doping profiles which can thus be realized are not as sharp as those which can be realized by means of the known, above-mentioned methods.
Surprisingly, it has been found that the method in accordance with the invention enables npn-transistors to be made which are suitable for processing signals of frequencies up to 40 GHz and which have a current amplification factor above 100. These transistors can thus suitably be used in integrated circuits for wireless communication systems. The heterojunction npn-transistors manufactured by means of the known, above-described methods are capable of processing signals of higher frequencies, however, said known methods enable only transistors of one type to be manufactured in a simple manner. Bipolar transistors which are made entirely of silicon and hence comprise base zones made of silicon to which no germanium is added can only be used in practice to process signals having frequencies up to 20 GHz.
If the second semiconductor layer of monocrystalline silicon with 5 to 25 at. % germanium is deposited in a thickness in the range from 10 to 30 nm, then the stresses in this semiconductor layer are so small that field-oxide regions can be formed in the three semiconductor layers by local oxidation of silicon. For this purpose, the wafer is heated, for example, for 1 hour in steam at a temperature of 1000° C. As a result, the germanium diffuses slightly from the second semicond
Magnee Petrus Hubertus Cornelis
Ponomarev Youri
Slotboom Jan Willem
Terpstra Doede
Van Rijs Freerk
Koninklijke Philips Electronics , N.V.
Nguyen Tuan H.
Waxler Aaron
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