Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-08-03
2002-09-10
Kim, Kenneth S. (Department: 2183)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C710S038000, C712S037000, C712S038000
Reexamination Certificate
active
06449740
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a single chip microcomputer and, more particularly, to a single chip microcomputer with a built-in EEPROM (Electrically Erasable and Programmable Read Only Memory).
DESCRIPTION OF THE RELATED ART
A central processing unit, a data memory, a program memory, a bus system and an interface are integrated on a single semiconductor chip, and is called as “single chip microcomputer”. The program memory is usually implemented by a mask ROM (Read Only Memory), and programmed instructions are stored in the mask ROM during the fabrication of the single chip microcomputer. A semiconductor wafer is divided into narrow areas, and the narrow areas are respectively assigned to individual products of the single chip microcomputer. Deposition steps, patterning steps, doping steps and other well-known steps are repeated for the fabrication of the single chip microcomputer, and the manufacturer obtains semimanufactured products of the single chip microcomputer. The mask ROM is incomplete in the semimanufactured products. An array of filed effect transistors forms the mask ROM, and is formed in the semimanufactured product of the single chip microcomputer. The mask ROM is programmed through a selective channel doping. The field effect transistors are selectively doped with a dopant impurity. Selected field effect transistors are changed to the normally-on type through the doping, and the others remain in the normally-off type. These two kinds of field effect transistors are corresponding to the two logic levels, and store programmed instructions in the mask ROM. Thus, the single chip microcomputer is unity, and the mask ROM is not separable from the other components. Moreover, the programmed instructions are non-rewritable.
The single chip microcomputer has found a wide variety of application. The control of power unit in the automobile is a typical example of the application. The single chip microcomputer forms an essential component part of a controlling unit, and the controlling unit is installed into the automobile. The single chip microcomputer sequentially executes the programmed instructions stored in the program memory, and controls the fuel injection, the revolution of the engine and so forth. A bug is not avoidable from the programmed instructions stored in the mask ROM. After the installation of the control unit into an automobile, the bug may be found. The automobile manufacturer announces the obligation to replace the control unit with a new one to the user. As described hereinbefore, the programmed instructions are non-rewritable, and the mask ROM is not separable from the single chip microcomputer. This means that the automobile manufacturer is to change the control unit with a new one. The replacement is a great expense.
In order to reduce the loss, the semiconductor manufacturer replaces the mask ROM with an EEPROM (Electrically Erasable and Programmable Read Only Memory). The EEPROM includes addressable memory cells, and the addressable memory cell is implemented by a floating gate type field effect transistor. When the manufacturer stores the programmed instructions into the memory cell array, electrons are selectively accumulated in the floating gates of the memory cells, and, accordingly, change the threshold of the selected memory cells. The high threshold and the low threshold are corresponding to the two logic levels, and the programmed instructions are stored in the form of different threshold in the memory cell array of the EEPROM.
The programmed instructions are erasable, new programmed instructions are stored in the memory cell array of the EEPROM. When the accumulated electrons are evacuated from the floating gates of the memory cells, the programmed instructions are erased from the memory cell array. After the erasing, electrons are selectively accumulated in the floating gates of the memory cells, again, and a set of new programmed instructions is stored in the memory cell array of the EEPROM. Although the program memory implemented by the EEPROM is not separable from the single chip microcomputer, the programmed instructions are rewritable. If a bug is found, the automobile manufacturer only rewrites the programmed instructions stored in the EEPROM, and the repairing work is not so expensive. For this reason, the single chip microcomputer with built-in EEPROM is in great demand.
The single chip microcomputer with built-in EEPROM has been improved in data processing capability, and a large program memory and a large data memory are required for complicated jobs. The data bus has been changed from 4 bits through 8 bits and 16 bits to 32 bits. The address lines have been also increased to 12 bits-32 bits, and the data storage capacity of the EEPROM is 1 kilobyte to 100 kilobytes. Thus, a large EEPROM is incorporated in the single chip microcomputer for the programmed instructions.
Upon completion of the fabrication process, the manufacturer checks the products to see whether or not all the components are operable without any trouble. The single chip microcomputer supplies an address signal from the central processing unit to the program memory, and the programmed instruction is supplied from the program memory to the central processing unit. Thus, the address signal and the programmed instruction are internally propagated between the components, and are not taken out from the single chip microcomputer. For this reason, the manufacturer tests the products before separation from the semiconductor wafer into the chips.
It is possible to carry out tests for the central processing unit, the random access memory, the interfaces/input/output ports and the timer within a short time. However, the test on the EEPROM consumes a long time. This is because of the fact that the injection of electron into a floating gate and the evacuation of electron therefrom are time-consuming. The testing system requires several milliseconds for each EEPROM cell, and the total time period for the EEPROM cell array is tens minutes. A semiconductor wafer is shared between products of the single chip microcomputer, and several hours are consumed for the tests on each semiconductor wafer. This results in low productivity. In the following description, the semiconductor chips before the separation of the semiconductor wafer are referred to as “semiconductor areas”.
The EEPROM is tested as follows. The first method is a diagnosis by using a built-in test circuit. The test circuit is integrated on the semiconductor area together with the other components during the fabrication process. The test circuit sequentially addresses the EEPROM cells, and writes a test pattern into the EEPROM cells. Thereafter, the test circuit reads out the test pattern, and compares the read-out test pattern with the write-in test pattern to see whether or not the EEPROM cells have maintained the test pattern without inversion of a test bit. When the read-out test pattern is consistent with the write-in test pattern, the test circuit outputs a diagnostic signal representative of the diagnosis.
A built-in test program is used in the second method. The central processing unit sequentially fetches the programmed instructions for the test, and executes the programmed instructions for generating an address signal and a test pattern. The address signal is supplied to the EEPROM cells so as to sequentially select the EEPROM cells from the cell array. The test pattern is written into the selected EEPROM cells. Upon completion of the write-in, the central processing unit sequentially addresses the EEPROM cells, and the test pattern is read out from the EEPROM cells. The read-out test pattern is compared with the write-in test pattern to see whether or not the EEPROM cells have maintained the test pattern without inversion of a test bit. When the read-out test pattern is consistent with the write-in test pattern, the central processing unit diagnoses the EEPROM cells as non-defective.
The third method is a diagnosis by using an external testing system. The testing system is equipped with
Hutchins, Wheeler & Dittmar
Kim Kenneth S.
NEC Corporation
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